Patents by Inventor Ana Claudia Arias
Ana Claudia Arias has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170156651Abstract: Pulse oximeter devices include a first light emitting element that emits red light, a second light emitting element that emits green light or IR light; and a sensor element that detects red and green (or IR) light and that outputs signals representing detected red and green (or IR) light. The pulse oximeter device further includes a flexible substrate, wherein the first light emitting element, the second light emitting element and the sensor element are formed on the flexible substrate. The sensor element is configured to detect the emitted red and green light transmitted through tissue containing blood, and in certain aspects, the sensor element is configured to detect the emitted red and green (or IR) light reflected by tissue containing blood. A signal processing element (e.g., a processor) receives and processes the signals representing detected red and green (or IR) light output by the sensor element to produce signals representing blood oxygenation content.Type: ApplicationFiled: January 24, 2017Publication date: June 8, 2017Inventors: Ana Claudia Arias, Claire Lochner, Adrien Pierre, Yasser Khan
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Publication number: 20170156658Abstract: Methods and apparatus for real-time, quantifiable monitoring of high-risk areas of biological tissue are described. The methods and apparatus use impedance spectroscopy to detect subtle changes in tissue health.Type: ApplicationFiled: December 14, 2016Publication date: June 8, 2017Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Michel Maharbiz, Vivek Subramanian, Ana Claudia Arias, Sarah Swisher, Amy Liao, Monica Lin, Felippe Pavinatto, Yasser Khan, Daniel Cohen, Elisabeth Leeflang, Shuvo Roy, Michael Harrison, David Young
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Patent number: 9666815Abstract: An embodiment is a method and apparatus to treat surface of polymer for printing. Surface of a polymer having a surface energy modified for a time period to control a feature characteristic and/or provide a hysteresis behavior. A material is printed on the surface to form a circuit pattern having at least one of the controlled feature characteristic and the hysteresis behavior.Type: GrantFiled: December 12, 2008Date of Patent: May 30, 2017Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Tse Nga Ng, Ana Claudia Arias, Jurgen H. Daniel
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Patent number: 9202683Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.Type: GrantFiled: December 2, 2013Date of Patent: December 1, 2015Assignee: Palo Alto Research Center IncorporatedInventors: Jurgen H. Daniel, Ana Claudia Arias
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Patent number: 9041123Abstract: A method and structures to achieve improved TFTs and high fill-factor pixel circuits are provided. This system relies on the fact that jet-printed lines have print accuracy, which means the location and the definition of the printed lines and dots is high. The edge of a printed line is well defined if the printing conditions are optimized. This technique utilizes the accurate definition and placement of the edges of printed lines of conductors and insulators to define small features and improved structures.Type: GrantFiled: January 6, 2014Date of Patent: May 26, 2015Assignee: Palo Alto Research Center IncorporatedInventors: Jurgen H. Daniel, Ana Claudia Arias
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Patent number: 9029245Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.Type: GrantFiled: December 2, 2013Date of Patent: May 12, 2015Assignee: Palo Alto Research Center IncorporatedInventors: Jurgen H. Daniel, Ana Claudia Arias
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Publication number: 20140210466Abstract: A Magnetic Resonance Imaging (MRI) receiver includes a receiver coil on a substrate. The receiver coil includes one or more capacitors. The construction of the capacitors allows for the use of very flexible substrates and allows the capacitors themselves to be highly flexible. The increased flexibility permits the MRI receiver to be conformed to the body of a patient and accordingly improves the MRI process.Type: ApplicationFiled: January 28, 2014Publication date: July 31, 2014Inventors: Ana Claudia Arias, Shimon Lustig, Anita M. Flynn, Joseph Corea
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Patent number: 8748242Abstract: A thin film transistor (TFT) structure is implemented. This embodiment is much less sensitive than conventional TFTs to alignment errors and substrate distortion. In such a configuration, there is no need to define gate features, so the layout is simplified. Moreover, the gate layer may be patterned by several inexpensive printing or non-printing methods.Type: GrantFiled: July 26, 2012Date of Patent: June 10, 2014Assignee: Palo Alto Research Center IncorporatedInventors: Jurgen H. Daniel, Ana Claudia Arias
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Publication number: 20140117448Abstract: A method and structures to achieve improved TFTs and high fill-factor pixel circuits are provided. This system relies on the fact that jet-printed lines have print accuracy, which means the location and the definition of the printed lines and dots is high. The edge of a printed line is well defined if the printing conditions are optimized. This technique utilizes the accurate definition and placement of the edges of printed lines of conductors and insulators to define small features and improved structures.Type: ApplicationFiled: January 6, 2014Publication date: May 1, 2014Applicant: Palo Alto Research Center IncorportedInventors: Jurgen H. Daniel, Ana Claudia Arias
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Patent number: 8709529Abstract: A light-emissive device comprising a light-emissive material provided between first and second electrodes such that charge carriers can move between the first and second electrodes and the light-emissive material, wherein the device includes a layer of a polymer blend provided between the first and second electrodes, phase separation of the polymers in the polymer blend having been induced in at least a portion of the polymer blend so as to control the propagation of light emitted by the light-emissive material in a predetermined direction.Type: GrantFiled: September 23, 2011Date of Patent: April 29, 2014Assignee: Cambridge Enterprise LtdInventors: J. Devin Mackenzie, Ana Claudia Arias, Richard Henry Friend, Wilhelm Huck
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Publication number: 20140094003Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.Type: ApplicationFiled: December 2, 2013Publication date: April 3, 2014Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Jurgen H. Daniel, Ana Claudia Arias
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Publication number: 20140087528Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.Type: ApplicationFiled: December 2, 2013Publication date: March 27, 2014Applicant: Palo Alto Research Center IncorporatedInventors: Jurgen H. Daniel, Ana Claudia Arias
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Patent number: 8680401Abstract: A printed circuit is produced with a base circuit and a number of optional circuit elements. One or more of the optional circuit elements may be added to the base circuit to determine or change the characteristics of the base circuit. Alternatively, one or more of the optional circuit elements may be removed from the base circuit to determine or change the characteristics of the base circuit. The base circuit and optional circuit elements may be printed on a single substrate. Mechanisms may be provided to facilitate the separation of the optional elements form the substrate either to introduce them into the base circuit or remove them from the base circuit to change the characteristics of the base circuit. A simple, low-cost, robust, and easy to use base circuit and optional circuit element is provided.Type: GrantFiled: December 8, 2010Date of Patent: March 25, 2014Assignee: Palo Alto Research Center IncorporatedInventors: Tse Nga Ng, Jurgen H. Daniel, Ana Claudia Arias, Brent Krusor
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Patent number: 8624330Abstract: A method and structures to achieve improved TFTs and high fill-factor pixel circuits are provided. This system relies on the fact that jet-printed lines have print accuracy, which means the location and the definition of the printed lines and dots is high. The edge of a printed line is well defined if the printing conditions are optimized. This technique utilizes the accurate definition and placement of the edges of printed lines of conductors and insulators to define small features and improved structures.Type: GrantFiled: November 26, 2008Date of Patent: January 7, 2014Assignee: Palo Alto Research Center IncorporatedInventors: Jurgen H. Daniel, Ana Claudia Arias
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Patent number: 8624304Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.Type: GrantFiled: May 16, 2012Date of Patent: January 7, 2014Assignee: Palo Alto Research Center IncorporatedInventors: Jurgen H. Daniel, Ana Claudia Arias
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Patent number: 8389346Abstract: The roughness and structural height of printed metal lines is used to pin a fluid. This fluid deposits a top contact material which is connected to the bottom printed contacts through pinholes in the hydrophobic polymer layer. This results in a sandwich-like contact structure achieved in a self-aligned deposition process and having improved source-drain contact for all-additive printed circuits. In one form, the present technique is used for thin film transistor applications, but it may be applied to electrodes in general.Type: GrantFiled: August 24, 2012Date of Patent: March 5, 2013Assignee: Palo Alto Research Center IncorporatedInventors: Jurgen H. Daniel, Ana Claudia Arias, Michael Chabinyc
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Publication number: 20120322214Abstract: The roughness and structural height of printed metal lines is used to pin a fluid. This fluid deposits a top contact material which is connected to the bottom printed contacts through pinholes in the hydrophobic polymer layer. This results in a sandwich-like contact structure achieved in a self-aligned deposition process and having improved source-drain contact for all-additive printed circuits. In one form, the present technique is used for thin film transistor applications, but it may be applied to electrodes in general.Type: ApplicationFiled: August 24, 2012Publication date: December 20, 2012Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Jürgen H. Daniel, Ana Claudia Arias, Michael Chabinyc
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Publication number: 20120302046Abstract: A thin film transistor (TFT) structure is implemented. This embodiment is much less sensitive than conventional TFTs to alignment errors and substrate distortion. In such a configuration, there is no need to define gate features, so the layout is simplified. Moreover, the gate layer may be patterned by several inexpensive printing or non-printing methods.Type: ApplicationFiled: July 26, 2012Publication date: November 29, 2012Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Jürgen H. Daniel, Ana Claudia Arias
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Patent number: 8288799Abstract: A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.Type: GrantFiled: March 21, 2012Date of Patent: October 16, 2012Assignee: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Ana Claudia Arias, Gregory Lewis Whiting
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Patent number: 8274084Abstract: The roughness and structural height of printed metal lines is used to pin a fluid. This fluid deposits a top contact material which is connected to the bottom printed contacts through pinholes in the hydrophobic polymer layer. This results in a sandwich-like contact structure achieved in a self-aligned deposition process and having improved source-drain contact for all-additive printed circuits. In one form, the present technique is used for thin film transistor applications, but it may be applied to electrodes in general.Type: GrantFiled: November 26, 2008Date of Patent: September 25, 2012Assignee: Palo Alto Research Center IncorporatedInventors: Jurgen H. Daniel, Ana Claudia Arias, Michael Chabinyc