Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.

Abstract: A process for fabricating fine features such as small gate electrodes on a transistor. The process involves the jet-printing of a mask and the plating of a metal to fabricate sub-pixel and standard pixel size features in one layer. Printing creates a small sub-pixel size gap mask for plating a fine feature. A second printed mask may be used to protect the newly formed gate and etch standard pixel size lines connecting the small gates.

Abstract: An embodiment is a method and apparatus to treat surface of polymer for printing. Surface of a polymer having a surface energy modified for a time period to control a feature characteristic and/or provide a hysteresis behavior. A material is printed on the surface to form a circuit pattern having at least one of the controlled feature characteristic and the hysteresis behavior.

Abstract: The roughness and structural height of printed metal lines is used to pin a fluid. This fluid deposits a top contact material which is connected to the bottom printed contacts through pinholes in the hydrophobic polymer layer. This results in a sandwich-like contact structure achieved in a self-aligned deposition process and having improved source-drain contact for all-additive printed circuits. In one form, the present technique is used for thin film transistor applications, but it may be applied to electrodes in general.

Abstract: A thin film transistor (TFT) structure is implemented. This embodiment is much less sensitive than conventional TFTs to alignment errors and substrate distortion. In such a configuration, there is no need to define gate features, so the layout is simplified. Moreover, the gate layer may be patterned by several inexpensive printing or non-printing methods.

Abstract: A method and structures to achieve improved TFTs and high fill-factor pixel circuits are provided. This system relies on the fact that jet-printed lines have print accuracy, which means the location and the definition of the printed lines and dots is high. The edge of a printed line is well defined if the printing conditions are optimized. This technique utilizes the accurate definition and placement of the edges of printed lines of conductors and insulators to define small features and improved structures.

Abstract: An electronic device comprising a thin film transistor (TFT) array and manufacturing methods thereof according to various embodiments. Jet-printed material is deposited on selected partially formed transistors to form completed transistors. Thus, a selected number of the TFTs are connected into the circuit while the remainder of the TFTs are not connected. An electronic read-out of the array identifies the specific array by distinguishing the connected TFTs from the unconnected ones. For a TFT array with n elements there are 2n alternative configurations; therefore, a relatively small number of TFTs can uniquely identify a huge number of devices. Such uniquely encoded devices have applications for encryption, identification and personalization of electronic systems.

Abstract: Photovoltaic devices (i.e., solar cells) are formed using non-contact patterning apparatus (e.g., a laser-based patterning systems) to define contact openings through a passivation layer, and direct-write metallization apparatus (e.g., an inkjet-type printing or extrusion-type deposition apparatus) to deposit metallization into the contact openings and over the passivation surface. The metallization includes two portions: a contact (e.g., silicide-producing) material is deposited into the contact openings, then a highly conductive metal is deposited on the contact material and between the contact holes. The device wafers are transported between the patterning and metallization apparatus in hard tooled registration using a conveyor mechanism. Optional sensors are utilized to align the patterning and metallization apparatus to the contact openings. An extrusion-type apparatus is used to form grid lines having a high aspect central metal line that is supported on each side by a transparent material.

Abstract: A backplane circuit includes an array of organic thin-film transistors (OTFTs), each OTFT including a source contact, a drain contact, and an organic semiconductor region extending between the source and drain contacts. The drain contacts in each row are connected to an address line. The source and drain contacts and the address lines are fabricated using a multi-layer structure including a relatively thick base portion formed of a relatively inexpensive metal (e.g., aluminum or copper), and a relatively thin contact layer formed of a high work function, low oxidation metal (e.g., gold) that exhibits good electrical contact to the organic semiconductor, is formed opposite at least one external surface of the base, and is located at least partially in an interface region where the organic semiconductor contacts an underlying dielectric layer.

Abstract: A method to pattern films into dimensions smaller than the printed pixel mask size. A printed mask is deposited on a thin film on a substrate. The second mask layer is selectively deposited onto the film, but not to the printed mask. A third mask is then printed onto the substrate to pattern a portion of the second mask. Certain solvents are then used to remove the printed mask but not the mask layer on the thin film. The mask layer is then used to form a pattern on the thin film in combination with etching. The features formed in the thin film are smaller than the smallest dimension of the printed mask. The coated mask layer can be a self-assembled mono-layer or other material that selectively binds to the thin film.

Abstract: A digital lithography system prints a large-area electronic device by dividing the overall device printing process into a series of discrete feature printing sub-processes, where each feature printing sub-process involves printing both a predetermined portion (feature) of the device in a designated substrate area, and an associated test pattern in a designated test area that is remote from the feature. At the end of each feature printing sub-process, the test pattern is analyzed, e.g., using a camera and associated imaging system, to verify that the test pattern has been successfully printed. A primary ejector is used until an unsuccessfully printed test pattern is detected, at which time a secondary (reserve) ejector replaces the primary ejector and reprints the feature associated with the defective test pattern. When multiple printheads are used in parallel, analysis of the test pattern is used to efficiently identify the location of a defective ejector.

Abstract: A transistor device is formed on a flexible substrate such that device processing remains at a low temperature. A first gate dielectric layer is formed over gate metal by annodization, eliminating relatively high-temperature dielectric deposition processes and difficulties with in-process substrate deformation. A second gate dielectric layer may optionally be provided over the first in order to provide an improved dielectric/semiconductor interface. A high performance pixel, and process for producing same, may thus be provided on a flexible substrate.

Abstract: A method for forming an aligned polymer layer, the method comprising: bringing a solution of the polymer dissolved in a solvent into contact with a substrate; and depositing the layer on the substrate by progressively absorbing molecules of the polymer from solution on to the substrate in the presence of a field capable of inducing alignment in the polymer; and separating the substrate from the solution.

Abstract: An electronic device comprising a layer of a polymer having an electrically conductive or semiconductive main chain, wherein the chains of the polymer have an electrically conductive or semiconductive charge transporting end-group at each end thereof, and the polymer in the layer is organised in a lamellar structure having ordered regions, in which the polymer main chains are aligned with respect to each other, and boundary regions which separate the ordered regions and in which the degree of alignment between adjacent polymer main chains is less than that in the ordered regions.

Abstract: A method for forming an aligned layer of a polymer, the method comprising: depositing a film of the polymer from solution in a solvent onto a substrate; and bringing the polymer into alignment by annealing the film at a temperature below the melting temperature of the polymer in isotropic bulk, and cooling the film.

Abstract: A light-emissive device comprising a light-emissive material provided between first and second electrodes such that charge carriers can move between the first and second electrodes and the light-emissive material, wherein the device includes a layer of a polymer blend provided between the first and second electrodes, phase separation of the polymers in the polymer blend having been induced in at least a portion of the polymer blend so as to control the propagation of light emitted by the light-emissive material in a predetermined direction.