Patents by Inventor Ana Claudia Arias
Ana Claudia Arias has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120238081Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.Type: ApplicationFiled: May 16, 2012Publication date: September 20, 2012Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Jurgen H. Daniel, Ana Claudia Arias
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Publication number: 20120235145Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.Type: ApplicationFiled: May 16, 2012Publication date: September 20, 2012Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Jurgen H. Daniel, Ana Claudia Arias
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Patent number: 8268725Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.Type: GrantFiled: October 7, 2010Date of Patent: September 18, 2012Assignee: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Robert A. Street, Ana Claudia Arias
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Patent number: 8253174Abstract: A thin film transistor (TFT) structure is implemented. This embodiment is much less sensitive than conventional TFTs to alignment errors and substrate distortion. In such a configuration, there is no need to define gate features, so the layout is simplified. Moreover, the gate layer may be patterned by several inexpensive printing or non-printing methods.Type: GrantFiled: November 26, 2008Date of Patent: August 28, 2012Assignee: Palo Alto Research Center IncorporatedInventors: Jurgen H. Daniel, Ana Claudia Arias
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Publication number: 20120175616Abstract: A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.Type: ApplicationFiled: March 21, 2012Publication date: July 12, 2012Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Sanjiv Sambandan, Ana Claudia Arias, Gregory Lewis Whiting
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Patent number: 8211782Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.Type: GrantFiled: October 23, 2009Date of Patent: July 3, 2012Assignee: Palo Alto Research Center IncorporatedInventors: Jurgen H. Daniel, Ana Claudia Arias
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Publication number: 20120146463Abstract: A printed circuit is produced with a base circuit and a number of optional circuit elements. One or more of the optional circuit elements may be added to the base circuit to determine or change the characteristics of the base circuit. Alternatively, one or more of the optional circuit elements may be removed from the base circuit to determine or change the characteristics of the base circuit. The base circuit and optional circuit elements may be printed on a single substrate. Mechanisms may be provided to facilitate the separation of the optional elements form the substrate either to introduce them into the base circuit or remove them from the base circuit to change the characteristics of the base circuit. A simple, low-cost, robust, and easy to use base circuit and optional circuit element is provided.Type: ApplicationFiled: December 8, 2010Publication date: June 14, 2012Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Tse Nga Ng, Jurgen H. Daniel, Ana Claudia Arias, Brent Krusor
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Patent number: 8164122Abstract: A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.Type: GrantFiled: September 21, 2011Date of Patent: April 24, 2012Assignee: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Ana Claudia Arias, Gregory Lewis Whiting
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Patent number: 8158465Abstract: A “vertical” coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a target structure in a solution made up of a fine particle solute dispersed in a liquid solvent such that a “waterline” is formed by the upper (liquid/air) surface of the solution on a targeted linear surface region of the substrate. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the straight-line portion of the substrate surface contacted by the receding waterline. The substrate and staining solution are selected such that the liquid solvent has a stronger attraction to the substrate surface than to itself to produce the required pinning and upward curving waterline. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.Type: GrantFiled: June 15, 2009Date of Patent: April 17, 2012Assignee: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Robert A. Street, Ana Claudia Arias
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Publication number: 20120064652Abstract: A light-emissive device comprising a light-emissive material provided between first and second electrodes such that charge carriers can move between the first and second electrodes and the light-emissive material, wherein the device includes a layer of a polymer blend provided between the first and second electrodes, phase separation of the polymers in the polymer blend having been induced in at least a portion of the polymer blend so as to control the propagation of light emitted by the light-emissive material in a predetermined direction.Type: ApplicationFiled: September 23, 2011Publication date: March 15, 2012Applicant: CAMBRIDGE ENTERPRISE LTDInventors: J. Devin Mackenzie, Ana Claudia Arias, Richard Henry Friend, Wilhelm Huck
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Publication number: 20120007079Abstract: A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.Type: ApplicationFiled: September 21, 2011Publication date: January 12, 2012Applicant: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Sanjiv Sambandan, Ana Claudia Arias, Gregory Lewis Whiting
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Patent number: 8053818Abstract: A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.Type: GrantFiled: December 18, 2009Date of Patent: November 8, 2011Assignee: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Ana Claudia Arias, Gregory Lewis Whiting
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Patent number: 8049406Abstract: A light-emissive device comprising a light-emissive material provided between first and second electrodes such that charge carriers can move between the first and second electrodes and the light-emissive material, wherein the device includes a layer of a polymer blend provided between the first and second electrodes, phase separation of the polymers in the polymer blend having been induced in at least a portion of the polymer blend so as to control the propagation of light emitted by the light-emissive material in a predetermined direction.Type: GrantFiled: April 12, 2002Date of Patent: November 1, 2011Assignee: Cambridge University Technical Services LimitedInventors: J. Devin Mackenzie, Ana Claudia Arias, Richard Henry Friend, Wilhelm Huck
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Publication number: 20110147742Abstract: A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.Type: ApplicationFiled: December 18, 2009Publication date: June 23, 2011Applicant: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Ana Claudia Arias, Gregory Lewis Whiting
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Patent number: 7964440Abstract: Composite films formed from blends of semiconducting and insulating materials that phase separate on patterned substrates are provided. Phase separation provides isolated and encapsulated areas of semiconductor on the substrate. Processes for preparing and using such composite films are also provided, along with devices including such composite films.Type: GrantFiled: December 20, 2004Date of Patent: June 21, 2011Assignee: Palo Alto Research Center IncorporatedInventors: Alberto Salleo, Ana Claudia Arias, William S. Wong
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Publication number: 20110095342Abstract: A first patterned contact layer, for example a gate electrode, is formed over an insulative substrate. Insulating and functional layers are formed at least over the first patterned contact layer. A second patterned contact layer, for example source/drain electrodes, is formed over the functional layer. Insulative material is then selectively deposited over at least a portion of the second patterned contact layer to form first and second wall structures such that at least a portion of the second patterned contact layer is exposed, the first and second wall structures defining a well therebetween. Electrically conductive or semiconductive material is deposited within the well, for example by jet-printing, such that the first and second wall structures confine the conductive or semiconductive material and prevent spreading and electrical shorting to adjacent devices. The conductive or semiconductive material is in electrical contact with the exposed portion of the second patterned contact layer to form, e.g.Type: ApplicationFiled: October 23, 2009Publication date: April 28, 2011Applicant: Palo Alto Research Center IncorporatedInventors: Jurgen H. Daniel, Ana Claudia Arias
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Patent number: 7897439Abstract: An electronic device comprising a thin film transistor (TFT) array and manufacturing methods thereof according to various embodiments. Jet-printed material is deposited on selected partially formed transistors to form completed transistors. Thus, a selected number of the TFTs are connected into the circuit while the remainder of the TFTs are not connected. An electronic read-out of the array identifies the specific array by distinguishing the connected TFTs from the unconnected ones. For a TFT array with n elements there are 2n alternative configurations; therefore, a relatively small number of TFTs can uniquely identify a huge number of devices. Such uniquely encoded devices have applications for encryption, identification and personalization of electronic systems.Type: GrantFiled: December 23, 2009Date of Patent: March 1, 2011Assignee: Palo Alto Research Center IncorporatedInventors: Robert A. Street, Ana Claudia Arias
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Publication number: 20110027946Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.Type: ApplicationFiled: October 7, 2010Publication date: February 3, 2011Applicant: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Robert A. Street, Ana Claudia Arias
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Patent number: 7867916Abstract: A modified coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a solution puddle on a target substrate, and then controlling the peripheral boundary shape of the puddle using a control structure that contacts the puddle's upper surface. The solution is made up of a fine particle solute dispersed in a liquid solvent wets and becomes pinned to both the target substrate and the control structure. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the target substrate surface that is contacted by the peripheral puddle boundary. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.Type: GrantFiled: June 15, 2009Date of Patent: January 11, 2011Assignee: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Robert A. Street, Ana Claudia Arias
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Publication number: 20100317159Abstract: A “vertical” coffee-stain method for producing self-organized line structures and other very fine features that involves disposing a target structure in a solution made up of a fine particle solute dispersed in a liquid solvent such that a “waterline” is formed by the upper (liquid/air) surface of the solution on a targeted linear surface region of the substrate. The solvent is then caused to evaporate at a predetermined rate such that a portion of the solute forms a self-organized “coffee-stain” line structure on the straight-line portion of the substrate surface contacted by the receding waterline. The substrate and staining solution are selected such that the liquid solvent has a stronger attraction to the substrate surface than to itself to produce the required pinning and upward curving waterline. The target structure is optionally periodically raised to generate parallel lines that are subsequently processed to form, e.g., TFTs for large-area electronic devices.Type: ApplicationFiled: June 15, 2009Publication date: December 16, 2010Applicant: Palo Alto Research Center IncorporatedInventors: Sanjiv Sambandan, Robert A. Street, Ana Claudia Arias