Patents by Inventor Andrew B. Kahng
Andrew B. Kahng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10713406Abstract: A method for optimizing a multi die implementation flow that is aware of mix-and-match die integration for implementing multi-die integrated circuits includes partitioning a netlist into partitions comprehending mix-and-match die integration, wherein each partition will be assigned to a die. Each partition is placed into a corresponding die. A clock tree of the integrated circuit is synthesized. Nets of the integrated circuit in are routed in accordance the placing and synthesizing.Type: GrantFiled: November 29, 2016Date of Patent: July 14, 2020Assignee: The Regents of the University of CaliforniaInventors: Andrew B. Kahng, Kwangsoo Han, Jiajia Li
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Publication number: 20180341738Abstract: A method for optimizing a multi die implementation flow that is aware of mix-and-match die integration for implementing multi-die integrated circuits includes partitioning a netlist into partitions comprehending mix-and-match die integration, wherein each partition will be assigned to a die. Each partition is placed into a corresponding die. A clock tree of the integrated circuit is synthesized. Nets of the integrated circuit in are routed in accordance the placing and synthesizing.Type: ApplicationFiled: November 29, 2016Publication date: November 29, 2018Inventors: Andrew B. Kahng, Kwangsoo Han, Jiajia Li
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Patent number: 9922161Abstract: Method for adjusting a layout used in making an integrated circuit includes one or more interconnects in the layout that are susceptible to dielectric breakdown are selected. One or more selected interconnects are adjusted to increase via to wire spacing with respect to at least one via and one wire of the one or more selected interconnects. Preferably, the selecting analyzes signal patterns of interconnects, and estimates the stress ratio based on state probability of routed signal nets in the layout. An annotated layout is provided that describes distances by which one or more via or wire segment edges are to be shifted. Adjustments can include thinning and shifting of wire segments, and rotation of vias.Type: GrantFiled: February 20, 2014Date of Patent: March 20, 2018Assignee: The Regents of the University of CaliforniaInventors: Andrew B. Kahng, Tuck Boon Chan
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Patent number: 9229686Abstract: A preferred method of accuracy configuration with an approximate adder receives two input operands and generates a first approximate adder output with a plurality of sub-adders having a first accuracy under a first condition. Error detection and correction is selectively enabled to generate a next approximate adder output having a second accuracy that is higher than the first accuracy under a second condition. In preferred embodiments, a pipelined architecture provides selectable stages and the enablement of each successive stage provides a high level of accuracy. Power gated control can achieve enablement of error correction stages to conserve power.Type: GrantFiled: August 27, 2012Date of Patent: January 5, 2016Assignee: The Regents of the University of CaliforniaInventors: Andrew B. Kahng, Seokhyeong Kang
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Publication number: 20150379188Abstract: Method for adjusting a layout used in making an integrated circuit includes one or more interconnects in the layout that are susceptible to dielectric breakdown are selected. One or more selected interconnects are adjusted to increase via to wire spacing with respect to at least one via and one wire of the one or more selected interconnects. Preferably, the selecting analyzes signal patterns of interconnects, and estimates the stress ratio based on state probability of routed signal nets in the layout. An annotated layout is provided that describes distances by which one or more via or wire segment edges are to be shifted. Adjustments can include thinning and shifting of wire segments, and rotation of vias.Type: ApplicationFiled: February 20, 2014Publication date: December 31, 2015Inventors: Andrew B. Kahng, Tuck Boon Chan
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Patent number: 9202003Abstract: Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology that changes a nominal gate-length of a transistor to a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length.Type: GrantFiled: April 4, 2014Date of Patent: December 1, 2015Assignee: Tela Innovations, Inc.Inventors: Puneet Gupta, Andrew B. Kahng
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Patent number: 9166567Abstract: A power-gating circuit and devices including the same are provided. The power-gating circuit includes a flip-flop configured to receive a first power supply voltage and a gated clock signal to operate and a switch circuit connected between a first power supply voltage source configured to supply the first power supply voltage and a second power supply voltage source configured to supply a second power supply voltage. The switch circuit includes a first switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to a clock enable signal and a second switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to the first power supply voltage.Type: GrantFiled: March 14, 2014Date of Patent: October 20, 2015Assignees: UNIVERSITY OF CALIFORNIA, SAN DIEGO, SAMSUNG ELECTRONICS CO., LTD.Inventors: Bong Il Park, Andrew B. Kahng, Seok Hyeong Kang, Jae Gon Lee
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Patent number: 9069926Abstract: Methods, layouts and chip design layouts that use annotations for communicating gate-length biasing amounts to post-layout tools are disclosed. One method includes receiving a chip design layout designed to includes select ones of a plurality of nominal cell layouts and an annotated cell layout. The chip design layout is defined by a plurality of layers and the plurality of nominal cell layouts define transistors, wherein each of the plurality of nominal cell layouts define nominal length transistors, and the annotated cell layout also defines transistors. The annotated cell layout is associated with an annotation layer that identifies a gate-length biasing to be applied to at least one transistor of the annotated cell layout. The gate-length biasing identifies an amount of change for a gate length and not width-sizing of a gate width of the at least one transistor of the annotated cell layout. The annotation layer is used to communicate design-specific directives that require implementation.Type: GrantFiled: May 5, 2014Date of Patent: June 30, 2015Assignee: Tela Innovations, Inc.Inventors: Puneet Gupta, Andrew B. Kahng
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Patent number: 8949768Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.Type: GrantFiled: September 14, 2012Date of Patent: February 3, 2015Assignee: Tela Innovations, Inc.Inventors: Puneet Gupta, Andrew B. Kahng
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Patent number: 8869094Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.Type: GrantFiled: September 14, 2012Date of Patent: October 21, 2014Assignee: Tela Innovations, Inc.Inventors: Puneet Gupta, Andrew B. Kahng
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Publication number: 20140266401Abstract: A power-gating circuit and devices including the same are provided. The power-gating circuit includes a flip-flop configured to receive a first power supply voltage and a gated clock signal to operate and a switch circuit connected between a first power supply voltage source configured to supply the first power supply voltage and a second power supply voltage source configured to supply a second power supply voltage. The switch circuit includes a first switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to a clock enable signal and a second switch configured to be connected between the first power supply voltage source and the second power supply voltage source and to operate in response to the first power supply voltage.Type: ApplicationFiled: March 14, 2014Publication date: September 18, 2014Inventors: Bong Il PARK, Andrew B. KAHNG, Seok Hyeong KANG, Jae Gon LEE
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Publication number: 20140245245Abstract: Methods, layouts and chip design layouts that use annotations for communicating gate-length biasing amounts to post-layout tools are disclosed. One method includes receiving a chip design layout designed to includes select ones of a plurality of nominal cell layouts and an annotated cell layout. The chip design layout is defined by a plurality of layers and the plurality of nominal cell layouts define transistors, wherein each of the plurality of nominal cell layouts define nominal length transistors, and the annotated cell layout also defines transistors. The annotated cell layout is associated with an annotation layer that identifies a gate-length biasing to be applied to at least one transistor of the annotated cell layout. The gate-length biasing identifies an amount of change for a gate length and not width-sizing of a gate width of the at least one transistor of the annotated cell layout. The annotation layer is used to communicate design-specific directives that require implementation.Type: ApplicationFiled: May 5, 2014Publication date: August 28, 2014Applicant: Tela Innovations, Inc.Inventors: Puneet Gupta, Andrew B. Kahng
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Publication number: 20140223404Abstract: Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology that changes a nominal gate-length of a transistor to a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length.Type: ApplicationFiled: April 4, 2014Publication date: August 7, 2014Applicant: Tela Innovations, Inc.Inventors: Puneet Gupta, Andrew B. Kahng
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Patent number: 8756555Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.Type: GrantFiled: September 14, 2012Date of Patent: June 17, 2014Assignee: Tela Innovations, Inc.Inventors: Puneet Gupta, Andrew B. Kahng
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Patent number: 8751974Abstract: The invention provides systems and methods for layout decomposition to produce exposure layouts that can be used to perform double patterning lithography (DPL). Preferred embodiment methods of the invention are executed by a computer and provide alternate methods for layout decomposition for double patterning lithography (DPL) using integer linear programming (ILP) formulations. Embodiments of the invention meet a key optimization goals, which is to reduce the total cost of layout decomposition, considering the abovementioned aspects that contribute to cost of prior conventional DPL techniques. Embodiments of the invention provide integer linear programming (ILP), phase conflict detection (PCD) and node election bipartization (NBD) formulations for the optimization of DPL layout decomposition, with a process-aware cost function that avoids small jogging line-ends, and maximizes overlap at dividing points of polygons. The cost function can also make preferential splits at landing pads, junctions and long runs.Type: GrantFiled: February 13, 2013Date of Patent: June 10, 2014Assignee: The Regents of the University of CaliforniaInventors: Andrew B. Kahng, Hailong Yao
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Publication number: 20140059105Abstract: A preferred method of accuracy configuration with an approximate adder receives two input operands and generates a first approximate adder output with a plurality of sub-adders having a first accuracy under a first condition. Error detection and correction is selectively enabled to generate a next approximate adder output having a second accuracy that is higher than the first accuracy under a second condition. In preferred embodiments, a pipelined architecture provides selectable stages and the enablement of each successive stage provides a high level of accuracy. Power gated control can achieve enablement of error correction stages to conserve power.Type: ApplicationFiled: August 27, 2012Publication date: February 27, 2014Applicant: The Regents of the University of CaliforniaInventors: Andrew B. Kahng, Seokhyeong Kang
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Patent number: 8635583Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.Type: GrantFiled: September 14, 2012Date of Patent: January 21, 2014Assignee: Tela Innovations, Inc.Inventors: Puneet Gupta, Andrew B. Kahng
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Publication number: 20130254734Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.Type: ApplicationFiled: September 14, 2012Publication date: September 26, 2013Inventors: Puneet Gupta, Andrew B. Kahng
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Patent number: 8490043Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.Type: GrantFiled: March 4, 2010Date of Patent: July 16, 2013Assignee: Tela Innovations, Inc.Inventors: Puneet Gupta, Andrew B. Kahng
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Patent number: 8402396Abstract: The invention provides systems and methods for layout decomposition to produce exposure layouts that can be used to perform double patterning lithography (DPL). Preferred embodiment methods of the invention are executed by a computer and provide alternate methods for layout decomposition for double patterning lithography (DPL) using integer linear programming (ILP) formulations. Embodiments of the invention meet a key optimization goals, which is to reduce the total cost of layout decomposition, considering the abovementioned aspects that contribute to cost of prior conventional DPL techniques. Embodiments of the invention provide integer linear programming (ILP), phase conflict detection (PCD) and node election bipartization (NBD) formulations for the optimization of DPL layout decomposition, with a process-aware cost function that avoids small jogging line-ends, and maximizes overlap at dividing points of polygons. The cost function can also make preferential splits at landing pads, junctions and long runs.Type: GrantFiled: September 28, 2010Date of Patent: March 19, 2013Assignee: The Regents of the University of CaliforniaInventors: Andrew B. Kahng, Hailong Yao