Abstract: A method for improving a resolution enhanced (RE) layout produced by an RE program that starts with a nominal integrated circuit layout. For at least one feature of said layout at least one critical feature quality is chosen from a set of feature qualities and at least one starting condition of said resolution enhancement program is adjusted in response to said at least one critical feature quality.

Abstract: A method for performing a mask design layout resolution enhancement includes determining a level of correction for the design layout for a predetermined parametric yield with a minimum total correction cost. The design layout is corrected at the determined level of correction based on a correction algorithm if the correction is required. In this manner, only those printed features on the design layout that are critical for obtaining the desired performance yield are corrected, thereby reducing the total cost of correction of the design layout.

Abstract: Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a transistor with a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. In an exemplary embodiment, the bias length is less than 10% of the nominal gate-length.

Abstract: Method for detecting hotspots in a circuit layout includes constructing a layout graph having nodes, corner edges and proximity edges from the circuit layout, converting the layout graph to a corresponding dual graph, and iteratively selecting edges and nodes having weights greater than a predetermined threshold value at each iteration as hotspots.

Abstract: A method for performing a mask design layout resolution enhancement includes determining a level of correction for a mask design layout for a predetermined parametric yield with a minimum total correction cost. The mask design layout is corrected at a determined level of correction based on a correction algorithm if the correction is required. In this manner, only those printed features on the mask design layout that are critical for obtaining a desired performance yield are corrected, thereby reducing total cost of correction of the mask design layout.

Abstract: A method and system for evaluating a floorplan and for defining a global buffered routing for an integrated circuit including constructing a graphical representation of the integrated circuit floorplan, including wire capacity and buffer capacity; formulating an integer linear program from said graphical representation; finding a solution to said integer linear program.

Abstract: A method for performing a mask design layout resolution enhancement includes determining a level of correction for the design layout for a predetermined parametric yield with a minimum total correction cost. The design layout is corrected at the determined level of correction based on a correction algorithm if the correction is required. In this manner, only those printed features on the design layout that are critical for obtaining the desired performance yield are corrected, thereby reducing the total cost of correction of the design layout.

Abstract: A method and system for evaluating a floorplan and for defining a global buffered routing for an integrated circuit including constructing a graphical representation of the integrated circuit floorplan, including wire capacity and buffer capacity; formulating an integer linear program from said graphical representation; finding a solution to said integer linear program.

Abstract: Disclosed is a diffusion-equation-based method of determining the time-domain response of an IC interconnect to an input voltage signal. Time-dependent voltage response determinations are accomplished analytically in the Laplace domain, with appropriate boundary conditions, treating the voltage response as a superposition of transmitted and reflected diffusions, based on parasitics as known quantities per unit length. The voltage response is thus determined by summing distinct reflected diffusions originating at both sides of the interconnect. The analysis proceeds on the assumption that only a selected small number of reflective components--normally only four--are required for sufficient accuracy. Voltage response from a sequence of interconnects is determined by treating the voltage response from the first interconnect as the input to the second, and repeating such looping with successive interconnects. A final inverse transform may be accomplished to express the response in the time domain.