Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

Abstract: Methods for generating a biased layout for making an integrated circuit are disclosed. One such method includes obtaining a nominal layout defined by one or more cells, where each cell has one or more transistor gate features with a nominal gate length. Then, obtaining an annotated layout. The annotated layout contains information describing gate-length biasing of one or more of the transistor gate features in one or more cells of the nominal layout. A biased layout is produced by modifying the nominal layout using the information from the annotated layout. The biasing modifies a gate length of those transistor gate features identified by the information of the annotated layout.

Abstract: Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology replaces a nominal gate-length of a transistor with a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. In an exemplary embodiment, the bias length is less than 10% of the nominal gate-length.

Abstract: An embodiment of the invention provides a tool for modifying a mask design layout to be printed. The tool is executed by a computer system, and includes code for establishing a first level of correction for a mask design layout for a predetermined parametric yield without cost of correction to area of the mask design layout. The tool also includes code for correcting the mask design layout at said first level of correction based on a correction algorithm, the correction algorithm selecting a cell of the mask design layout having an edge placement error (EPE) for each gate feature in the cell. The correction algorithm selects the cell without loss to parametric yield as established by the predetermined parametric yield.

Abstract: Systems of the invention employ peer-to-peer and centralized server networking to enable POTS/PSTN/PBX phone lines to be shared with other users of the system over the Internet. An example application of the invention is to allow a person, having access to an Internet connection, to receive calls and make calls using his/her home or office telephone, or using the phones of other parties that he/she is authorized to access. In preferred embodiments, the invention can exploit availability of an existing voice modem port on the user's home or office computer, and can require only the installation of software on the home or office computer, and on whatever device (laptop, PDA, computer, mobile phones, etc.) is employed by the user in the remote location.

Abstract: Method for detecting hotspots in a circuit layout includes constructing a layout graph having nodes, corner edges and proximity edges from the circuit layout, converting the layout graph to a corresponding dual graph, and iteratively selecting edges and nodes having weights greater than a predetermined threshold value at each iteration as hotspots.

Abstract: The invention provides systems and methods for layout decomposition to produce exposure layouts that can be used to perform double patterning lithography (DPL). Preferred embodiment methods of the invention are executed by a computer and provide alternate methods for layout decomposition for double patterning lithography (DPL) using integer linear programming (ILP) formulations. Embodiments of the invention meet a key optimization goals, which is to reduce the total cost of layout decomposition, considering the abovementioned aspects that contribute to cost of prior conventional DPL techniques. Embodiments of the invention provide integer linear programming (ILP), phase conflict detection (PCD) and node election bipartization (NBD) formulations for the optimization of DPL layout decomposition, with a process-aware cost function that avoids small jogging line-ends, and maximizes overlap at dividing points of polygons. The cost function can also make preferential splits at landing pads, junctions and long runs.

Abstract: Method and apparatus for designing an integrated circuit. A new layout is generated for at least one standard cell that incorporates an auxiliary pattern on a gate layer to facilitate cell-based optical proximity correction. An original placement solution is modified for a plurality of standard cells to permit incorporation of cells containing auxiliary patterns while improving an objective function of a resulting placement solution for the plurality of standard cells.

Abstract: A method of using a static performance analyzer that accepts as input a cell-level netlist, to perform static performance analysis on a circuit represented by a transistor level netlist. The method begins with converting said transistor-level netlist to a cell-level netlist by modeling individual transistors with a cell model. Then, a static performance analyzer is used to perform a static performance analysis of said cell-level netlist. Among performance characteristics that may be analyzed are timing (static timing analysis) and leakage power. The method described may also be used for statistical static timing and power analysis.

Abstract: A method of designing a digital circuit is described, so that it is likely to pass a signoff time test. The method begins with the running of a basic static time test on a partially developed version of the digital circuit, next a signoff time test is run for the partially developed version of the digital system. The differences between the results of the basic static time test and the signoff time test are noted and the prospective basic static time test passing conditions are altered so that if a similar system passes the basic static time test with the altered passing conditions it will be more likely to pass the signoff time test. Then, the partially developed version of the digital system is altered to yield a second partially developed version and the first static time test is run, with the altered passing conditions on the second partially developed version.

Abstract: The present invention provides a method and system for improving reticle enhancement calculations during manufacture of an integrated circuit (IC). The reticle enhancement calculations are improved by incorporating post-planarization topography estimates. A planarization process of a wafer layer is simulated to estimate the post-planarization topography. RET calculations, such as sub-resolution assist feature insertion, optical proximity corrections and phase shifting are then performed based on the post-planarization topography of the wafer layer.

Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

Abstract: Methods for generating a biased layout for making an integrated circuit are disclosed. One such method includes obtaining a nominal layout defined by one or more cells, where each cell has one or more transistor gate features with a nominal gate length. Then, obtaining an annotated layout. The annotated layout contains information describing gate-length biasing of one or more of the transistor gate features in one or more cells of the nominal layout. A biased layout is produced by modifying the nominal layout using the information from the annotated layout. The biasing modifies a gate length of those transistor gate features identified by the information of the annotated layout.

Abstract: An integrated circuit having a metal interconnect layer, and also having a conductive line and a boundary defined with a uniform distance from the conductive line that defines a “keep out” distance between the boundary and the conductive line. A set of first fill elements are uniformly arranged along the boundary outside of the “keep out” distance, and a set of second fill elements further from the conductive line than the first fill elements are arranged in a pattern that would be uniform, but for having some fill elements missing from the pattern.

Abstract: The present invention provides a method and a system for designing an integrated circuit comprising a plurality of elements. The method includes obtaining a lithography-simulated layout corresponding to at least one element. The lithography-simulated layout accounts for lithography effects on the element. The method further includes determination of an equivalent circuit representation that is compatible to a circuit analysis tool, corresponding to the lithography-simulated layout with respect to one or more performance characteristics and based on user preferences. The method also provides equivalent circuit representation to the circuit analysis tool that analyzes one or more performance characteristics of the elements.

Abstract: Computer readable media hosting a layout description of electric circuitry that includes a description of prospective fill units and includes characteristic data noting at least one characteristic of each fill unit. In one preferred embodiment, each prospective fill unit includes just a single prospective fill element. Also, in a preferred embodiment, said characteristic data includes effect on electrical characteristics of nearby electrical circuitry. These electrical characteristics may further include timing characteristics and capacitance characteristics. The effect on the thickness of nearby connective elements also may be noted.

Abstract: An embodiment of the invention provides a tool for modifying a mask design layout to be printed. The tool is executed by a computer system, and includes code for establishing a first level of correction for a mask design layout for a predetermined parametric yield without cost of correction to area of the mask design layout. The tool also includes code for correcting the mask design layout at said first level of correction based on a correction algorithm, the correction algorithm selecting a cell of the mask design layout having an edge placement error (EPE) for each gate feature in the cell. The correction algorithm selects the cell without loss to parametric yield as established by the predetermined parametric yield.

Abstract: A method and system for detailed placement of layout objects in a standard-cell layout design are disclosed. Layout objects comprise cells and etch dummies. The method includes a programming based technique to calculate layout object perturbation distances for the layout objects. The method includes adjusting the layout objects with their corresponding layout object perturbation distances. This leads to improved photolithographic characteristics such as reduced Critical Dimension (CD) errors and forbidden pitches in the standard-cell layout.