Patents by Inventor Andrew Caldwell
Andrew Caldwell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150186561Abstract: A method of optimizing timing performance of an IC design is provided. The IC design is expressed as a graph that includes a plurality of paths. Each path includes a plurality of nodes that represent IC components including clocked elements and computational elements. The method optimizes the timing performance of the IC design by retiming a set of paths. The retiming includes skewing clock signals to a set of clocked elements by more than a clock period without changing the position of any clocked element relative to the position of the computational elements in the set of paths. The method performs simulation on the optimized IC design and provides the result of the simulation as a clock skew scheduling of the IC design instead of retiming of the IC design.Type: ApplicationFiled: December 24, 2014Publication date: July 2, 2015Inventors: Steven Teig, Andrew Caldwell
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Publication number: 20150154332Abstract: Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.Type: ApplicationFiled: November 26, 2014Publication date: June 4, 2015Inventors: Brad Hutchings, Andrew Caldwell, Steven Teig
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Patent number: 9041430Abstract: An integrated circuit (IC) with a novel configurable routing fabric is provided. The configurable routing fabric has signal paths that propagate signals between user registers on user clock cycles. Each signal path includes a set of configurable storage elements and a set of configurable logic elements. Each configurable storage element in the path is reconfigurable on every sub-cycle of the user clock cycle to either store an incoming signal or to pass the incoming signal transparently.Type: GrantFiled: January 28, 2014Date of Patent: May 26, 2015Assignee: TABULA, INC.Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell
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Publication number: 20150135148Abstract: An abstract decision module primitive for placement within a logical representation (i.e., a netlist) of a circuit design is described. The decision module primitive receives as inputs alternative solutions for a given function or segment of a netlist. The alternative solutions include functionally equivalent, but structurally different implementations of the function or segment of the netlist. The decision module primitive alternatively selects between connecting one of the inputs to the netlist to provide a complete functional definition for the netlist based on constraint information. The selected input of the decision module may be updated as additional constraint information is determined throughout the various stages of the design process. In addition, alternative solutions for a given function or segment of the netlist may be added to and/or removed from the inputs of a decision module as additional constraint information is identified.Type: ApplicationFiled: November 10, 2014Publication date: May 14, 2015Inventors: Andrew Caldwell, Steven Teig
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Patent number: 9000801Abstract: An integrated circuit (IC) that includes multiple clock domains is provided. Each clock domain operates at a user specified data rate, and the data rates of at least two of the clock domains are related by a common base clock. The specified data rate of each clock domain is controlled by a modulating signal. Each clock domain includes reconfigurable circuits that operate on the common base clock, and the modulating signal controls the data rate of the clock domain by modulating reconfiguration of the reconfigurable circuits. The reconfigurable circuits reconfigure when the modulating signal enables the reconfiguration.Type: GrantFiled: March 13, 2013Date of Patent: April 7, 2015Assignee: Tabula, Inc.Inventors: Christopher D. Ebeling, Michael Glenn Wrighton, Andrew Caldwell, Kent Townley
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Publication number: 20150082261Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.Type: ApplicationFiled: April 7, 2014Publication date: March 19, 2015Applicant: Tabula, Inc.Inventors: Andrew Caldwell, Herman Schmit, Steven Teig
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Publication number: 20150067807Abstract: Measures for operating a user device in a telecommunications network. In a browser on the user device, a password associated with a given telephony service identifier is stored in a browser cache associated with the browser. A user of the user device has one or more telephony service identifiers, including the given telephony service identifier, allocated by a service provider for conducting communication services in the network. In the browser on the user device, in response to receipt of user input via the browser indicative of a request to conduct communications using the given telephony service identifier, the stored password is retrieved from the browser cache and used to authenticate the user device for at least one communication service in the network using the given telephony service identifier.Type: ApplicationFiled: August 26, 2014Publication date: March 5, 2015Inventors: Matthew WILLIAMS, Keith WANSBROUGH, Andrew CALDWELL
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Publication number: 20150040094Abstract: Some embodiments provide a method of designing an integrated circuit (IC). The design is expressed as a graph that includes several nodes that represent several IC components. The nodes include a first set of nodes that represent a set of clocked elements. The method creates a second set of nodes by removing all nodes in the first set from the nodes that represent the IC components. The method identifies a set of edges that connect two nodes in the second set without encompassing a third node in the second set. The method assigns an event time to each node in the second set. The method assigns a cost function based on the event times of the nodes connected by each edge and the number of nodes in the first set encompassed by each edge. The method optimizes the cost function and places the components based on the cost function optimization.Type: ApplicationFiled: August 15, 2014Publication date: February 5, 2015Inventors: Andrew Caldwell, Steven Teig
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Patent number: 8935647Abstract: An abstract decision module primitive for placement within a logical representation (i.e., a netlist) of a circuit design is described. The decision module primitive receives as inputs alternative solutions for a given function or segment of a netlist. The alternative solutions include functionally equivalent, but structurally different implementations of the function or segment of the netlist. The decision module primitive alternatively selects between connecting one of the inputs to the netlist to provide a complete functional definition for the netlist based on constraint information. The selected input of the decision module may be updated as additional constraint information is determined throughout the various stages of the design process. In addition, alternative solutions for a given function or segment of the netlist may be added to and/or removed from the inputs of a decision module as additional constraint information is identified.Type: GrantFiled: August 31, 2013Date of Patent: January 13, 2015Assignee: Tabula, Inc.Inventors: Andrew Caldwell, Steven Teig
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Patent number: 8935640Abstract: Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design.Type: GrantFiled: April 17, 2013Date of Patent: January 13, 2015Assignee: Tabula, Inc.Inventors: Brad Hutchings, Andrew Caldwell, Steven Teig
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Publication number: 20140333345Abstract: Some embodiments provide a configurable integrated circuit (IC) having a routing fabric that includes configurable storage element in its routing fabric. In some embodiments, the configurable storage element includes a parallel distributed path for configurably providing a pair of transparent storage elements. The pair of configurable storage elements can configurably act either as non-transparent (i.e., clocked) storage elements or transparent configurable storage elements. In some embodiments, the configurable storage element in the routing fabric performs both routing and storage operations by a parallel distributed path that includes a clocked storage element and a bypass connection. In some embodiments, the configurable storage element perform both routing and storage operations by a pair of master-slave latches but without a bypass connection.Type: ApplicationFiled: May 19, 2014Publication date: November 13, 2014Applicant: Tabula, Inc.Inventors: Martin Voogel, Steven Teig, Thomas S. Chanack, Andrew Caldwell, Jung Ko, Trevis Chandler
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Publication number: 20140323083Abstract: Measures for processing communication status messages in a telecommunications network which includes a plurality of signaling nodes responsible for processing signaling information in the telecommunications network and a charging node responsible for processing billing information in the telecommunications network. A communication status message is received from a signaling node in the plurality. The received communication status message includes first communication status information. Second communication status information is generated on the basis of at least the first communication status information. One or more communication status messages are transmitted to the charging node. The one or more transmitted communication status messages include the first communication status information and the second communication status information.Type: ApplicationFiled: April 30, 2014Publication date: October 30, 2014Applicant: Metaswitch Networks LtdInventors: Andrew CALDWELL, Michael Jeffrey EVANS, Martin TAYLOR
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Publication number: 20140317588Abstract: Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions has one reconfigurable circuit perform a particular configurable operation in at least two reconfiguration cycles while the other identified solution does not have one reconfigurable circuit perform the particular configurable operation in two reconfiguration cycles. The method costs the first and second physical design solutions. The method selects one of the two physical design solutions based on the costs.Type: ApplicationFiled: April 25, 2014Publication date: October 23, 2014Applicant: Tabula, Inc.Inventors: Steven Teig, Andrew Caldwell
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Patent number: 8863067Abstract: Some embodiments provide a method of designing an integrated circuit (IC). The design is expressed as a graph that includes several nodes that represent several IC components. The nodes include a first set of nodes that represent a set of clocked elements. The method creates a second set of nodes by removing all nodes in the first set from the nodes that represent the IC components. The method identifies a set of edges that connect two nodes in the second set without encompassing a third node in the second set. The method assigns an event time to each node in the second set. The method assigns a cost function based on the event times of the nodes connected by each edge and the number of nodes in the first set encompassed by each edge. The method optimizes the cost function and places the components based on the cost function optimization.Type: GrantFiled: February 6, 2008Date of Patent: October 14, 2014Assignee: Tabula, Inc.Inventors: Andrew Caldwell, Steven Teig
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Publication number: 20140272882Abstract: Systems and methods for detecting aberrant behavior in a testing environment involve receiving real-time audio-visual data from a detection device and executing an application stored in memory that, when executed by a processor, detect aberrant data within the real-time audio-visual data and reacting automatically to the aberrant data.Type: ApplicationFiled: March 13, 2014Publication date: September 18, 2014Applicant: Kryterion, Inc.Inventors: James Kaufman, Andrew Caldwell
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Publication number: 20140240001Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit.Type: ApplicationFiled: January 28, 2014Publication date: August 28, 2014Applicant: Tabula, Inc.Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell
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Publication number: 20140210512Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.Type: ApplicationFiled: January 28, 2014Publication date: July 31, 2014Applicant: Tabula, Inc.Inventors: Scott J. Weber, Christopher D. Ebeling, Andrew Caldwell, Steven Teig, Timothy J. Callahan, Hung Q. Nguyen, Shangzhi Sun, Shilpa V. Yeole
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Patent number: 8788987Abstract: A novel method for designing an integrated circuit (“IC”) by rescaling an original set of circuits in a design of the IC is disclosed. The original set of circuits to be rescaled includes sequential nodes, combinational nodes, and interconnects. Each sequential node is associated with a phase of a clock. The method generates a rescaled set of circuits that includes multiple replica sets of the circuits. Each replica set of circuits includes sequential nodes, combinational nodes, and interconnects that are identical to nodes and interconnects in the original set of circuits. Each sequential node is associated with a phase of a clock that is at a fraction of the phase of its corresponding sequential element in the original set. The method connects nodes in each replica set of circuits to a logically equivalent node in another replica set. The method replaces the original set of circuits with the rescaled set of circuits.Type: GrantFiled: April 6, 2011Date of Patent: July 22, 2014Assignee: Tabula, Inc.Inventors: Scott J. Weber, Christopher D. Ebeling, Andrew Caldwell, Steven Teig, Timothy J. Callahan, Hung Q. Nguyen, Shangzhi Sun, Shilpa V. Yeole
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Patent number: 8760193Abstract: An integrated circuit (“IC”) having configurable logic circuits for configurably performing multiple different logic operations based on configuration data is provided. The IC includes a row of the configurable logic circuits and multiple configuration retrieval circuits for providing configuration bits to the row of configurable logic circuits. The IC also includes a row configuration controller for forcing the multiple configuration retrieval circuits to output a particular configuration value based on a user signal that is received at runtime.Type: GrantFiled: July 2, 2012Date of Patent: June 24, 2014Assignee: Tabula, Inc.Inventors: Martin Voogel, Steven Teig, Thomas S. Chanack, Andrew Caldwell, Jung Ko, Trevis Chandler
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Patent number: 8756547Abstract: Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions has one reconfigurable circuit perform a particular configurable operation in at least two reconfiguration cycles while the other identified solution does not have one reconfigurable circuit perform the particular configurable operation in two reconfiguration cycles. The method costs the first and second physical design solutions. The method selects one of the two physical design solutions based on the costs.Type: GrantFiled: March 26, 2012Date of Patent: June 17, 2014Assignee: Tabula, Inc.Inventors: Steven Teig, Andrew Caldwell