Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit.

Abstract: Some embodiments provide a reconfigurable IC that implements a design that is designed at a particular design clock rate. The reconfigurable IC includes reconfigurable circuits for performing operations on a set of inputs in the particular design. The IC further includes routing circuits for routing signals to and from the logic circuits to allow the logic circuits to perform the operations. The reconfigurable IC implements the design by having reconfigurable circuits that reconfigure at a rate faster than the design clock rate. For at least one operation which is defined at the design clock rate, the reconfigurable IC replicates the operation set in at least two reconfiguration cycles to reduce consumption of routing circuits.

Abstract: An abstract decision module primitive for placement within a logical representation (i.e., a netlist) of a circuit design is described. The decision module primitive receives as inputs alternative solutions for a given function or segment of a netlist. The alternative solutions include functionally equivalent, but structurally different implementations of the function or segment of the netlist. The decision module primitive alternatively selects between connecting one of the inputs to the netlist to provide a complete functional definition for the netlist based on constraint information. The selected input of the decision module may be updated as additional constraint information is determined throughout the various stages of the design process. In addition, alternative solutions for a given function or segment of the netlist may be added to and/or removed from the inputs of a decision module as additional constraint information is identified.

Abstract: An abstract decision module primitive for placement within a logical representation (i.e., a netlist) of a circuit design is described. The decision module primitive receives as inputs alternative solutions for a given function or segment of a netlist. The alternative solutions include functionally equivalent, but structurally different implementations of the function or segment of the netlist. The decision module primitive alternatively selects between connecting one of the inputs to the netlist to provide a complete functional definition for the netlist based on constraint information. The selected input of the decision module may be updated as additional constraint information is determined throughout the various stages of the design process. In addition, alternative solutions for a given function or segment of the netlist may be added to and/or removed from the inputs of a decision module as additional constraint information is identified.

Abstract: Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit.

Abstract: A process for preparing a perfume composition, the process having the steps of; (a) contacting a perfume ingredient with a molten material to form a pre-mix; (b) contacting the pre-mix with a first solid material to form a soft-solid intermediate high active perfume material; (c) solidifying the molten material to form a hardened-solid intermediate high active perfume material; (d) contacting the hardened-solid intermediate high active perfume intermediate material with a second solid material to form a perfume composition, wherein the ratio of the wt % amount of perfume ingredient present in the hardened-solid intermediate high active perfume material to the wt % amount of perfume ingredient present in the perfume composition is greater than 1.5:1.

Abstract: The present invention relates to a process for preparing a spray-dried powder comprising (i) anionic detersive surfactant; (ii) from 0 wt % to 10 wt % zeolite builder; (iii) from 0 wt % to 10 wt % phosphate builder; and (iv) optionally from 0 wt % to 15 wt % silicate salt; wherein the process comprises the steps of: (a) forming an alkaline slurry in a mixer, the slurry having a viscosity of from X to Y s?1 at a temperature of 70° C.

Abstract: The present invention relates to a process for preparing a spray-dried powder comprising (i) anionic detersive surfactant; (ii) from 0 wt % to 10 wt % zeolite builder; (iii) from 0 wt % to 10 wt % phosphate builder; and (iv) optionally from 0 wt % to 15 wt % silicate salt; wherein the process comprises the steps of: (a) forming an alkaline slurry in a mixer, the slurry comprising: (v) from 0 wt % to 15 wt % anionic detersive surfactant; (vi) from 0 wt % to 35 wt % water; and (b) transferring the alkaline slurry from the mixer through at least one pump to a spray pressure nozzle; (c) contacting an acid anionic detersive surfactant precursor to the alkaline slurry after the mixer and before the spray pressure nozzle to form a mixture; (d) spraying the mixture through the spray pressure nozzle into a spray-drying tower; (e) spray-drying the mixture to form a spray-dried powder; and (f) optionally, contacting an alkalinity source with the alkaline slurry and/or the acid anionic detersive surfactant precursor, and

Abstract: Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions on a set of inputs. The IC also includes several input select interconnect circuits for selecting the input set supplied to each configurable logic circuit. Each input select interconnect circuit is associated with a particular configurable logic circuit. When a configurable logic circuit is used to perform a multiplication operation, at least one of its associated input select interconnect circuits performs a logic operation that implements part of the multiplication operation.

Abstract: A plow device is disclosed. The plow device comprises a blade and a plurality of struts attached to the blade. Each strut comprises an arm comprising a first end and a second end. Each arm being attached to the blade at its first end. Each strut further comprising a tire wedge disposed at the second end of the arm.

Abstract: Some embodiments provide a method of presenting virtual memory as narrower and deeper than a physical memory. The method receives a memory address location including a set of real memory address bits and a set of virtual memory position bits. The method retrieves an original memory word from a physical memory using the real memory address bits. The method shifts the original memory word by an amount determined by the virtual memory position bits by using a barrel shifter, creating a shifted memory word. The method reads a part of the shifted memory word.

Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit.

Abstract: The present invention relates to a process for preparing a spray-dried powder comprising (i) anionic detersive surfactant; (ii) from 0 wt % to 10 wt % zeolite builder; (iii) from 0 wt % to 10 wt % phosphate builder; and (iv) optionally from 0 wt % to 15 wt % silicate salt; wherein the process comprises the steps of: (a) forming an alkaline slurry in a mixer, the slurry having a viscosity of from X to Y s?1 at a temperature of 70° C.

Abstract: Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions has one reconfigurable circuit perform a particular configurable operation in at least two reconfiguration cycles while the other identified solution does not have one reconfigurable circuit perform the particular configurable operation in two reconfiguration cycles. The method costs the first and second physical design solutions. The method selects one of the two physical design solutions based on the costs.

Abstract: Some embodiments provide a method of performing circuit synthesis that receives a design that has a function with several inputs. The method identifies a set of early arriving inputs of the function and performs a function decomposition on the function based on one of the early arriving inputs. In some embodiments, the method estimates the number of circuits a signal has to travel through to reach each input of the function and selects a set of inputs with signals that travel through fewer numbers of circuits compared to signals of inputs that are not selected. In some embodiments in which the design has more than a particular number of inputs, the method recursively identifies early arriving signals and performs function decomposition until function decomposition results in a set of functions all of which with fewer than the particular number of inputs. In some embodiments, the function decomposition is Shannon decomposition.

Abstract: Some embodiments provide a configurable integrated circuit with a tile. The tile has a first input multiplexer (IMUX), a second IMUX, and a look up table (LUT). The first IMUX is configured as a two-input multiplexer. The second IMUX is also configured as a two-input multiplexer. The LUT is also configured as a third two-input multiplexer. An output of the first IMUX is connected to the first input of the LUT, an output of the second IMUX is connected to the second input of the LUT. A third input of the LUT accepts a selection bit.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.

Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.