Abstract: An integrated circuit (IC) die includes a plurality of ferroelectric tunnel junction (FTJ) devices, where at least one FTJ of the plurality of FTJ devices comprises first electrode, a second electrode, ferroelectric material disposed between the first and second electrodes, and interface material disposed between at least one of the first and second electrodes and the ferroelectric material. Other embodiments are disclosed and claimed.

Abstract: An embodiment of an integrated circuit (IC) device may include a plurality of layers of wide bandgap (WBG)-based circuitry and a plurality of layers of silicon (Si)-based circuitry monolithically bonded to the plurality of layers of WBG-based circuitry, with one or more electrical connections between respective WBG-based circuits in the plurality of layers of WBG-based circuitry and Si-based circuits in the plurality of layers of Si-based circuitry. In some embodiments, a wafer-scale WBG-based IC is hybrid bonded or layer transfer bonded to a wafer-scale Si-based IC. Other embodiments are disclosed and claimed.

Abstract: Embodiments disclosed herein include a photonics module and methods of forming photonics modules. In an embodiment, the photonics module comprises a waveguide, and a modulator adjacent to the waveguide. In an embodiment, the modulator comprises a PN junction with a P-doped region and an N-doped region, where the PN junction is vertically oriented so that the P-doped region is over the N-doped region.

Abstract: An integrated circuit (IC) die includes a plurality of varactor devices, where at least one varactor of the plurality of varactor devices comprises a first electrode, a second electrode, and a multi-layer stack of ferroelectric material (e.g., ferroelectric variable capacitance material) disposed between the first and second electrodes. Other embodiments are disclosed and claimed.

Abstract: An integrated circuit (IC) die includes a plurality of front-side metallization layers including a first front-side metallization layer and one or more additional front-side metallization layers, a plurality of back-side metallization layers formed on the plurality front side metallization layers including a first back-side metallization layer and one or more additional back-side metallization layers, wherein the first front-side metallization layer is proximate to the first back-side metallization layer, and a vertical metallization structure formed through at least the first front-side metallization layer and the first back-side metallization layer, wherein the vertical metallization structure electrically connects a first metallization structure on one of the one or more additional front-side metallization layers to a second metallization structure on one of the one or more additional back-side metallization layers. Other embodiments are disclosed and claimed.

Abstract: A wireless communication system serves a wireless User Equipment (UE) over a wireless network slice. A serving wireless communication network selects a Uniform Data Repository (UDR) in a target wireless communication network based on the wireless network slice. The serving wireless communication network transfers an information request for the wireless UE across a wireless communication network boundary to the selected UDR in the target wireless communication network. In response to the information request, the selected UDR in the target wireless communication network transfers UE information for the wireless UE across the wireless communication network boundary to the serving wireless communication network. The wireless network slice in the serving wireless communication network serves the wireless UE based on the UE information.

Abstract: An integrated circuit die includes a first conductive structure for an input of a capacitively coupled device, a second conductive structure aligned with the first conductive structure for a signal to be capacitively coupled to the input of the capacitively coupled device, a first insulator material disposed between the first conductive structure and the second conductive structure, wherein the first insulator material comprises high gain insulator material, and a cooling structure operable to remove heat from the capacitively coupled device to achieve an operating temperature at or below 0° C. Other embodiments are disclosed and claimed.

Abstract: Embodiments of the present disclosure are directed to systems and methods for improving wireless network services by carrying out various procedures to identify and filter suspect user devices. A network function may monitor a plurality of network service requests from a particular user device and determine, based on the plurality of network services requests, that the requesting user device is engaged in suspicious activity. Upon such a determination, the network function may initiate one or more enforcement actions by communicating an instruction to an equipment identity register to add the requesting user device to a suspect device list stored on a unified data repository.

Abstract: Disclosed are various embodiments facilitating a holistic engagement with a user across multiple communication channels of an organization or an enterprise based at least in part on a determined user intent. As users interact with various services associated with the organization through one or more communication channels, interaction data can be captured and stored. In various examples, the interaction data that is stored by the various services can be obtained and organized according to a predefined schema. The organized interaction data can be applied to a trained intent model that outputs a user intent based at least in part on observations of other users with similar histories. The predicted intent can be provided to the different services such that subsequent interactions between the user and the organization can be based at least in part on the intent in a consistent manner, regardless of the communication channel associated with the interaction.

Abstract: In one embodiment, a system for managing communication connections in a virtualization environment includes a plurality of host machines implementing a virtualization environment, wherein each of the host machines includes a hypervisor, at least one user virtual machine (user VM), and a distributed file server that includes file server virtual machines (FSVMs) and associated local storage devices. Each FSVM and associated local storage device are local to a corresponding one of the host machines, and the FSVMs conduct I/O transactions with their associated local storage devices based on I/O requests received from the user VMs. Each of the user VMs on each host machine sends each of its representative I/O requests to an FSVM that is selected by one or more of the FSVMs for each I/O request based on a lookup table that maps a storage item referenced by the I/O request to I/O the selected one of the FSVMs.

Abstract: Systems and methods for border gateway protocol (BGP) Segment Routing (SR) (BGP-SR) update packing include negotiating with border gateway protocol (BGP) peers for packing BGP-Segment Routing (BGP-SR) updates, receiving a plurality of prefixes for a BGP-SR update message, encoding the plurality of prefixes with associated label information in network layer reachability information (NLRI) of the BGP-SR update message, and transmitting the BGP-SR update message to any of the BGP peers.

Abstract: A system is provided for producing composite products including a substrate and a resin integrated with the substrate.

Abstract: Bits are stored in an array with multiple capacitors sharing a single access transistor and a common plate coupled to the transistor. A single common select transistor accesses information stored in an array of capacitors, above and below the transistor and sharing a common plate. The common plate may be vertical and encircled by each of the other plates. The capacitors may be ferroelectric capacitors. In an integrated circuit system, the array may be coupled to a power supply and a cooling structure.

Abstract: Structures having airgaps for backside signal routing or power delivery are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a plurality of nanowire-based transistors, and a plurality of metallization layers above the nanowire-based transistors of the device layer. A backside structure is below the nanowire-based transistors of the device layer. The backside structure includes a first conductive line laterally spaced apart from a second conductive line by an air gap.

Abstract: Stacked static random-access memory (SRAM) circuits have doubled word length for a given SRAM cell area. An integrated circuit (IC) die includes stacked SRAM cells in vertically adjacent device layers with access transistors connected to a common wordline. The IC die with stacked SRAM cells having a common word line may be attached to a substrate and coupled to a power supply and, advantageously, to an active-cooling structure. SRAM cells may be formed in vertically adjacent layers of a substrate and electrically connected at their access transistor gate electrodes.

Abstract: Structures having recessed channel transistors are described. In an example, an integrated circuit structure includes a channel structure having a recess extending partially there through. A gate dielectric layer is on a bottom and along sides of the recess, the gate dielectric layer laterally surrounded by the channel structure. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below and uppermost surface of the channel structure.

Abstract: Bits are stored in an array with multiple capacitors per access transistor. An array of multiple ferroelectric capacitors shares a nanowire or nanosheet as a common plate and stores information accessed by a single common select transistor, which uses the nanowire or nanosheet for its channel. In an integrated circuit (IC) system, a group of bitlines is connected to a capacitor array by arrays of nanowires or nanosheets and wordline-controlled non-planar transistors. An IC die with a capacitor array accessed by a single select transistor and sharing a nanowire or nanosheet is coupled to a power supply and a cooling structure.

Abstract: Structures having memory access transistors with backside contacts are described. In an example, an integrated circuit structure includes a front-side structure including a device layer having a fin-based transistor, and a capacitor structure above the fin-based transistor of the device layer. A backside structure is below the front-side structure. The backside structure includes a conductive contact electrically connected to the fin-based transistor of the device layer.

Abstract: Structures having raised epitaxy on channel structure transistors are described. In an example, an integrated circuit structure includes a channel structure having multi-layer epitaxial source or drain structures thereon, the multi-layer epitaxial source or drain structures having a recess extending there through. A gate dielectric layer is on a bottom and along sides of the recess and laterally surrounded by the epitaxial source or drain structures. A gate electrode is on and laterally surrounded by the gate dielectric layer. The gate electrode has an uppermost surface below an uppermost surface of the gate dielectric layer.

Abstract: Bits are stored in an array with multiple storage elements sharing a single access transistor and a storage line coupled to the transistor. A single common select transistor accesses information stored in an array of storage elements. Other arrays of storage elements on parallel storage lines can be coupled into a crosspoint array by source lines orthogonal to the storage lines. The storage elements may be non-volatile. In an integrated circuit system, the array may be coupled to a power supply and a cooling structure.