Abstract: An integrated circuit includes a first conductive structure, a second conductive structure, and a first spacer and a second spacer each comprising a first dielectric material. The integrated circuit further includes a layer comprising a second dielectric material that is compositionally different from the first dielectric material. The integrated circuit further includes a first interconnect feature above and at least partially landed on the first conductive structure. In an example, the first interconnect feature is laterally between the first spacer and the second spacer. The integrated circuit further includes a second interconnect feature above and at least partially landed on the second conductive structure. In an example, the second interconnect feature is laterally between the second spacer and the layer comprising the second dielectric material.

Abstract: Computer-implemented methods and systems described herein are directed to reducing volumes of log messages sent from edge systems to a data center. The computer-implemented methods performed at each edge system includes collecting a stream of log messages generated by one or more event sources of the edge system. Representative log messages of the stream of log messages are determined. The edge systems may discard non-representative log messages from data storage devices at the edge system. The representative log messages are sent from each of the edge systems to the data center where the representative log messages are received and stored in data storage devices of the data center, thereby reducing the volumes of log messages sent from the edge systems to the data center.

Abstract: Stitched dies having a cooling structure are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region. A common conductive interconnection is coupling the first die and the second die at a first side of the first and second dies. A plurality of microfluidic channels is coupled to the first side of the first and second dies.

Abstract: Stitched dies having high bandwidth and capacity are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer, wherein the first device layer is a logic device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the first die by a scribe region. The second device layer is a transistor device layer, and the second plurality of metallization layers includes a layer of capacitor structures between an upper metallization layer portion and a lower metallization layer portion. A common conductive interconnection is coupling the first die and the second die at a first side of the first and second dies.

Abstract: Stitched dies having backside power delivery are described are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region. A signal line is coupling the first die and the second die at a first side of the first and second dies. A backside power rail is coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side.

Abstract: Integrated circuits with embedded memory that includes ferroelectric capacitors having first conductor structures coupled to an underlying array of access transistors, and second conductors coupled to independent plate lines that are shunted by a metal strap having a pitch similar to that of the capacitors. The independent plate lines may reduce bit-cell disturbs and/or simplify read/write process while the plate line straps reduce series resistance of the plate lines. The metal straps may be subtractively patterned lines in direct contact with the second capacitor conductors, or may be damascene structures coupled to the second capacitor conductors through vias that also have a pitch similar to that of the capacitors.

Abstract: Integrated circuits with embedded memory that includes ferroelectric capacitors having first conductor structures coupled to an underlying array of access transistors, and second conductors coupled to independent plate lines that are shunted by a metal strap having a pitch similar to that of the capacitors. The independent plate lines may reduce bit-cell disturbs and/or simplify read/write process while the plate line straps reduce series resistance of the plate lines. The metal straps may be subtractively patterned lines in direct contact with the second capacitor conductors, or may be damascene structures coupled to the second capacitor conductors through vias that also have a pitch similar to that of the capacitors.

Abstract: Integrated circuits with embedded memory having multiple levels. Each memory array level includes ferroelectric capacitors coupled to an array of thin film access transistors according to a 1T-1F or 1T-many F bit-cell architecture. The levels of embedded memory are monolithically fabricated, one over the other, or after monolithically fabricating one level of embedded memory in a host IC structure, a second IC structure with another level of memory array is directly bonded to a front or backside of the host IC structure in a face-to-face or face-to-back orientation. The second IC structure may include additional peripheral CMOS circuitry, such as sense amps or decoders, or not.

Abstract: Integrated circuits with embedded memory that includes double-walled ferroelectric capacitors over an array of access transistors. Capacitor access transistors may be recessed channel array transistors (RCATs) implemented in a monocrystalline material that has been transferred from a donor wafer, or implemented in an amorphous or polycrystalline semiconductor material that has been deposited, such as a metal oxide semiconductor.

Abstract: The current document is directed to a resource-exchange system that facilitates resource exchange and sharing among computing facilities. The currently disclosed methods and systems employ efficient, distributed-search methods and subsystems within distributed computer systems that include large numbers of geographically distributed data centers to locate resource-provider computing facilities that match the resource needs of resource-consumer computing-facilities based on attribute values associated with the needed resources, the resource providers, and the resource consumers. The resource-exchange system organizes and tracks operations related to a resource exchange using a resource-exchange context.

Abstract: Techniques are provided for forming one or more thermoelectric devices integrated within a substrate of an integrated circuit. Backside substrate processing may be used to form adjacent portions of the substrate that are doped with alternating dopant types (e.g., n-type dopants alternating with p-type dopants). The substrate can then be etched to form pillars of the various n-type and p-type portions. Adjacent pillars of opposite dopant type can be electrically connected together via a conductive layer. Additionally, the top portions of adjacent pillars are connected together, and the bottom portions of a next pair of adjacent pillars being coupled together, in a repeating pattern to ensure that current flows through the length of each of the doped pillars. The flow of current through alternating n-type and p-type doped material creates a heat flux that transfers heat from one end of the integrated thermoelectric device to the other end.

Abstract: A workflow construction system for constructing automation workflows that automate user specific processes. The workflow construction system may include a template library including workflow templates and pre-configured attributes. The workflow template can accelerate the design and construction of custom automation workflows. An orchestration layer included in the workflow construction system will also improve the performance of systems that execute the automation workflows by dynamically scaling the processing capacity, memory, and storage of servers and other systems hosting the model file instances of the automation workflows to ensure the available resources meet the demands of users completing processes using the automation workflows.

Abstract: An orchestration layer for execution user defined automation workflows. The orchestration layer may include multiple process instances that host user defined automation workflows that automate processes or tasks. To improve system performance and reduce operating costs, the user defined automation workflows are deployed to the orchestration layer in a standard format that standardizes the user defined workflow configurations. The orchestration layer may also dynamically scale the computational resources allocated to teach process instance based on the properties of each user defined automation workflow.

Abstract: A workflow construction system for constructing automation workflows that automate user specific processes. The workflow construction system may include a template library including workflow templates and pre-configured attributes. The workflow template can accelerate the design and construction of custom automation workflows. An orchestration layer included in the workflow construction system will also improve the performance of systems that execute the automation workflows by dynamically scaling the processing capacity, memory, and storage of servers and other systems hosting the model file instances of the automation workflows to ensure the available resources meet the demands of users completing processes using the automation workflows.

Abstract: A workflow construction system for constructing automation workflows that automate user specific processes. The workflow construction system may include a template library including workflow templates and pre-configured attributes. The workflow template can accelerate the design and construction of custom automation workflows. An orchestration layer included in the workflow construction system will also improve the performance of systems that execute the automation workflows by dynamically scaling the processing capacity, memory, and storage of servers and other systems hosting the model file instances of the automation workflows to ensure the available resources meet the demands of users completing processes using the automation workflows.

Abstract: A workflow automation system that automates business tasks by executing task workflow models. The workflow automation system distributes actions to multiple clients based on roles and permissions to facilitate completion of manual and automated tasks included in the workflow models. The workflow automation system may pre-configure the roles and permissions to reduce the set up time for workflow model implementations of tasks. The workflow automation system improves the speed and efficiency of completing tasks relative to manual methods and other workflow automation tools.

Abstract: The current document is directed a resource-exchange system that facilitates resource exchange and sharing among computing facilities. The currently disclosed methods and systems employ efficient, distributed-search-based auction methods and subsystems within distributed computer systems that include large numbers of geographically distributed data centers to locate resource-provider computing facilities that match the resource needs of resource-consumer computing facilities. Multiple security methods and subsystems are employed to prevent unauthorized access to resource-exchange-system services, to secure resource-exchange-system-participant data from unauthorized access, and to prevent hosted virtual machines and other hosted computational entities from interfering with operation of native virtual machines and other native computational entities within hosting resource-provider computing facilities.

Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.

Abstract: Disclosed herein are systems and methods for replicating data across deployments in a routing constrained environment. To replicate data, a processor may detect a modification that changes data for a source entity within a source environment hosting a source deployment of an application. The processor may then update a target environment hosting a target deployment of the application to mirror the modification within the source environment. To update the target environment, the processor may generate a mapping artifact that identifies the source entity having changed data and the target entity within the target environment receiving the changed data. The processor may then create a mapping infrastructure including one or more compute instances that replicate the changed data for the source entity in the target entity.

Abstract: Computer-implemented methods and systems described herein are directed to reducing volumes of log messages sent from edge systems to a data center. The computer-implemented methods performed at each edge system includes collecting a stream of log messages generated by one or more event sources of the edge system. Representative log messages of the stream of log messages are determined. The edge systems may discard non-representative log messages from data storage devices at the edge system. The representative log messages are sent from each of the edge systems to the data center where the representative log messages are received and stored in data storage devices of the data center, thereby reducing the volumes of log messages sent from the edge systems to the data center.