Patents by Inventor Anthony Dip

Anthony Dip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070231757
    Abstract: A gas delivery system for supplying a process gas from a gas supply to a thermal processing furnace, a thermal processing furnace equipped with the gas delivery system, and methods for delivering process gas to a thermal processing furnace. The gas delivery system comprises a plurality of regulators, such as mass flow controllers, in a process gas manifold coupling a gas supply with a thermal processing furnace. The regulators establish a corresponding plurality of flows of a process gas at a plurality of flow rates communicated by the process gas manifold to the thermal processing furnace. The gas delivery system may be a component of the thermal processing furnace that further includes a liner that surrounds a processing space inside the thermal processing furnace.
    Type: Application
    Filed: March 29, 2006
    Publication date: October 4, 2007
    Applicant: Tokyo Electron Limited
    Inventors: Anthony Dip, Eric Malstrom
  • Patent number: 7235440
    Abstract: Ultra-thin oxide layers are formed utilizing low pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxide. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, a nitride layer, a high-k layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or, alternatively, using a single-wafer process chamber. One embodiment of the invention provides self-limiting oxidation of Si-substrates that results in SiO2 layers with a thickness of about 15 A, where the thickness of the SiO2 layers varies less than about 1 A over the substrates.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: June 26, 2007
    Assignees: Tokyo Electron Limited, International Business Machines Corporation
    Inventors: David L O'Meara, Cory Wajda, Anthony Dip, Michael Toeller, Toshihara Furukawa, Kristen Scheer, Alessandro Callegari, Fred Buehrer, Sufi Zafar, Evgeni Gousev, Anthony Chou, Paul Higgins
  • Patent number: 7205187
    Abstract: A method is provided for depositing a silicon-containing film in a micro-feature on a substrate by a low pressure deposition process in a processing system. A silicon-containing film can be formed in a micro-feature by providing a substrate in a process chamber of a processing system, and exposing a hexachlorodisilane (HCD) process gas to the substrate. A processing tool containing a processing system for forming a silicon-containing film in a micro-feature using a silicon and chlorine-containing gas such as a HCD process gas is provided. Alternatively, the micro-feature can be exposed to DCS, SiCl4, and SiHCl3 gases. Alternatively, the micro-feature can be exposed to (SiH4+HCl).
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: April 17, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Allen John Leith, Anthony Dip, Seungho Oh
  • Patent number: 7202186
    Abstract: Ultra-thin oxynitride layers are formed utilizing low-pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, or a nitride layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or a single-wafer process chamber.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: April 10, 2007
    Assignees: Tokyo Electron Limited, International Business Machines Corporation (IBM)
    Inventors: David L O'Meara, Cory Wajda, Anthony Dip, Michael Toeller, Toshihara Furukawa, Kristen Scheer, Alessandro Callegari, Fred Buehrer, Sufi Zafar, Evgeni Gousev, Anthony Chou, Paul Higgins
  • Publication number: 20070048956
    Abstract: A method is provided for selectively forming a Si-containing film on a substrate in an interrupted deposition process. The method includes providing a substrate containing a growth surface and a non-growth surface, and selectively forming the Si-containing film on the growth surface by exposing the substrate to HX gas while simultaneously exposing the substrate to a pulse of chlorinated silane gas. The Si-containing film can be a Si film or a SiGe film that is selectively formed on a Si or SiGe growth surface but not on an oxide, nitride, or oxynitride non-growth surface.
    Type: Application
    Filed: August 30, 2005
    Publication date: March 1, 2007
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Anthony Dip, Seungho Oh, Allen Leith
  • Publication number: 20070042569
    Abstract: A method for selectively forming an epitaxial Si containing film on a semiconductor structure at low temperature. The method includes providing the structure in a process chamber, the structure containing a Si substrate having an epitaxial Si surface area and a patterned film area thereon. A Si film is non-selectively deposited onto the structure, the Si film comprising an epitaxial Si film deposited onto the epitaxial Si surface and a non-epitaxial Si film deposited onto an exposed surface of the patterned film. The non-epitaxial Si film is selectively dry etched away to form a patterned epitaxial Si film. The Si film may be a SiGe film.
    Type: Application
    Filed: August 18, 2005
    Publication date: February 22, 2007
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Anthony Dip, Allen Leith, Seungho Oh
  • Publication number: 20070042570
    Abstract: A method is provided for forming a Si film in sequential deposition process. The method includes providing a substrate in a process chamber, forming a chlorinated Si film by exposing the substrate to a chlorinated silane gas, and dry etching the chlorinated Si film to reduce the chlorine content of the Si film. The Si film may be deposited selectively or non-selectively on the substrate and the deposition may be self-limiting or non-self-limiting. Other embodiments provide a method for forming SiGe films in a sequential deposition process.
    Type: Application
    Filed: August 18, 2005
    Publication date: February 22, 2007
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Anthony Dip, Allen Leith, Seungho Oh
  • Publication number: 20070039924
    Abstract: A method and system for processing a substrate includes providing the substrate in a process chamber, the substrate having an oxide layer formed thereon, and exposing the substrate to an etching gas containing F2 gas at a first temperature to remove the oxide layer from the substrate. The substrate may subsequently be heated to a second temperature greater than the first temperature, and a film may then be formed on the substrate at the second temperature. In one embodiment, a Si film is epitaxially formed on a Si substrate.
    Type: Application
    Filed: August 18, 2005
    Publication date: February 22, 2007
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Anthony Dip, Allen Leith, Seungho Oh
  • Publication number: 20070037412
    Abstract: An in situ method for forming a HfO2 high-k dielectric layer in a batch wafer processing system. The method comprises first loading a plurality of wafers into a process chamber, and then pre-treating the plurality of wafers in the process chamber with a first oxidizer. After pre-treating the wafers, and without removing the wafers from the process chamber, the method then comprises depositing HfO2 on the plurality of wafers by atomic layer deposition, which comprises a plurality of deposition cycles, each cycle comprising alternating exposure of the plurality of wafers in the process chamber to a second oxidizer and a hafnium precursor. The hafnium precursor is selected from hafnium tert-butoxide (HTB) or hafnium tetra-diethylamide (TDEAH).
    Type: Application
    Filed: August 3, 2006
    Publication date: February 15, 2007
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Anthony Dip, Sadao Sasaki, Michael Toeller, Kimberly Reid
  • Patent number: 7165011
    Abstract: A method of monitoring a thermal processing system in real-time using a built-in self test (BIST) table that includes positioning a plurality of wafers in a processing chamber in the thermal processing system; executing a real-time dynamic model to generate a predicted dynamic process response for the processing chamber during the processing time; creating a first measured dynamic process response; determining a dynamic estimation error using a difference between the predicted dynamic process response and the measured dynamic process response; and comparing the dynamic estimation error to operational thresholds established by one or more rules in the BIST table.
    Type: Grant
    Filed: September 1, 2005
    Date of Patent: January 16, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Sanjeev Kaushal, Pradeep Pandey, Kenji Sugishima, Anthony Dip, David Smith, Raymond Joe, Sundar Gandhi
  • Patent number: 7141765
    Abstract: A antireflective film 50 is formed on a thermocouple 42 arranged in a processing vessel 1 of a heat treatment apparatus in order to improve the transient response characteristics of the thermocouple 42. In a typical embodiment, the thermocouple 42 is made by connecting a platinum wire 43A and a platinum-rhodium alloy wire 43B, and the antireflective film 50 is composed by stacking a silicon nitride layer 50C, silicon layer 50B and a silicon nitride layer 50A in that order.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: November 28, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Toshiyuki Makiya, Takanori Saito, Karuki Eickmann, Sanjeev Kaushal, Anthony Dip, David L. O'meara
  • Publication number: 20060228900
    Abstract: A method and system for processing a substrate includes providing the substrate in a process chamber, where the substrate contains an oxide layer formed thereon, exciting a hydrogen-containing gas in a remote plasma source coupled to the process chamber, and exposing the substrate to a flow of the excited hydrogen-containing gas at a first substrate temperature lower than about 900° C. to remove the oxide layer from the substrate. The substrate is then maintained at a second temperature different than the first substrate temperature, and a silicon-containing film is formed on the substrate at the second substrate temperature.
    Type: Application
    Filed: March 31, 2005
    Publication date: October 12, 2006
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Anthony Dip, Allen Leith, Seungho Oh
  • Publication number: 20060160288
    Abstract: A method is provided for depositing a silicon-containing film in a micro-feature on a substrate by a low pressure deposition process in a processing system. A silicon-containing film can be formed in a micro-feature by providing a substrate in a process chamber of a processing system, and exposing a hexachlorodisilane (HCD) process gas to the substrate. A processing tool containing a processing system for forming a silicon-containing film in a micro-feature using a silicon and chlorine-containing gas such as a HCD process gas is provided. Alternatively, the micro-feature can be exposed to DCS, SiCl4, and SiHCl3 gases. Alternatively, the micro-feature can be exposed to (SiH4+HCl).
    Type: Application
    Filed: January 18, 2005
    Publication date: July 20, 2006
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Allen Leith, Anthony Dip, Seungho Oh
  • Patent number: 7022192
    Abstract: A semiconductor wafer susceptor for batch substrate processing. The susceptor includes a central region in a primary plane and a plurality of flat annular extensions extending below the central region in a secondary plane. The primary and secondary planes are parallel to each other. An edge of the substrate overhangs the central region allowing no contact of the susceptor with the substrate edge.
    Type: Grant
    Filed: September 4, 2002
    Date of Patent: April 4, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Anthony Dip, Takanori Saito, Raymond Joe
  • Publication number: 20050221001
    Abstract: A method for extending time between chamber cleaning processes in a process chamber of a processing system. A particle-reducing film is formed on a chamber component in the process chamber to reduce particle formation in the process chamber during substrate processing, at least one substrate is introduced into the process chamber, a manufacturing process is performed in the process chamber, and the at least one substrate is removed from the process chamber. The particle-reducing film may be deposited on a clean chamber component or on a material deposit formed on a chamber component. Alternatively, the particle-reducing film may be formed by chemically modifying at least a portion of a material deposit on a chamber component. The particle-reducing film may be formed after each manufacturing process or at selected intervals after multiple manufacturing processes.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 6, 2005
    Applicant: Tokyo Electron Limited of TBS Broadcast Center
    Inventors: Raymond Joe, John Gumpher, Anthony Dip
  • Publication number: 20050217799
    Abstract: A wafer heating assembly is described having a unique heater element for use in a single wafer processing systems. The heating unit includes a carbon wire element encased in a quartz sheath. The heating unit is as contamination-free as the quartz, which permits direct contact to the wafer. The mechanical flexibility of the carbon ‘wire’ or ‘braided’ structure permits a coil configuration, which permits independent heater zone control across the wafer. The multiple independent heater zones across the wafer can permit temperature gradients to adjust film growth/deposition uniformity and rapid thermal adjustments with film uniformity superior to conventional single wafer systems and with minimum to no wafer warping. The low thermal mass permits a fast thermal response that enables a pulsed or digital thermal process that results in layer-by-layer film formation for improved thin film control.
    Type: Application
    Filed: March 31, 2004
    Publication date: October 6, 2005
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: David O'Meara, Gerrit Leusink, Stephen Cabral, Anthony Dip, Cory Wajda, Raymond Joe
  • Publication number: 20050199872
    Abstract: A SiGe thin layer semiconductor structure containing a substrate having a dielectric layer, a variable composition SixGe1-x layer on dielectric layer, and a Si cap layer on the variable composition SixGe1-x layer. The variable composition SixGe1-x layer can contain a SixGe1-x layer with a graded Ge content or a plurality of SixGe1-x sub-layers each with different Ge content. In one embodiment of the invention, the SiGe thin layer semiconductor structure contains a semiconductor substrate having a dielectric layer, a Si-containing seed layer on the dielectric layer, a variable composition SixGe1-x layer on the seed layer, and a Si cap layer on the variable composition SixGe1-x layer. A method and processing tool for fabricating the SiGe thin layer semiconductor structure are also provided.
    Type: Application
    Filed: March 10, 2004
    Publication date: September 15, 2005
    Applicant: Tokyo Electron Limited of TBS Broadcast Center
    Inventors: Pradip Roy, Anthony Dip, Allen Leith, Seungho Oh
  • Publication number: 20050199877
    Abstract: A method for using a silicon germanium (SiGe) surface layer to integrate a high-k dielectric layer into a semiconductor device. The method forms a SiGe surface layer on a substrate and deposits a high-k dielectric layer on the SiGe surface layer. An oxide layer, located between the high-k dielectric layer and an unreacted portion of the SiGe surface layer, is formed during one or both of deposition of the high-k dielectric layer and an annealing process after deposition of the high-k dielectric layer. The method further includes forming an electrode layer on the high-k dielectric layer.
    Type: Application
    Filed: March 10, 2004
    Publication date: September 15, 2005
    Applicant: Tokyo Electron Limited of TBS Broadcast Center
    Inventors: Anthony Dip, Pradip Roy, Sanjeev Kaushal, Allen Leith, Seungho Oh, Raymond Joe
  • Publication number: 20050066892
    Abstract: A method is provided for depositing a silicon-containing film on a substrate by a low pressure deposition process in a processing system. A silicon-containing film can be formed on a substrate by providing a substrate in a process chamber of a processing system, heating the substrate, and exposing a hexachlorodisilane (HCD) process gas to the substrate. The method can selectively deposit an epitaxial silicon-containing film on a silicon surface of a substrate or, alternately, non-selectively deposit a silicon-containing film on a substrate. A processing tool containing a processing system for forming a silicon-containing film on s substrate using a HCD process gas is provided.
    Type: Application
    Filed: September 30, 2003
    Publication date: March 31, 2005
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Anthony Dip, Seungho Oh, Allen Leith
  • Patent number: 6869892
    Abstract: A method of oxidizing work pieces according to the present invention comprises the steps of: containing a plurality of work pieces W in a processing vessel 22 which has a predetermined length and is capable forming a vacuum therein, oxidizing surfaces of the work pieces in an atmosphere including active oxygen species and active hydroxyl species which are generated by supplying an oxidative gas and a reductive gas into the processing vessel to interact the gases. The oxidative gas and the reductive gas are respectively supplied into the processing vessel in the longitudinal direction. Parts of the reductive gas are additionally supplied from at least two or more independently controlled gas nozzles located at separate locations in the longitudinal direction of the processing vessel. The gas flow rate through each nozzle is set depending on any combination of the work pieces composed of product wafers, dummy wafers, and monitor wafers in the processing vessel.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: March 22, 2005
    Assignees: Tokyo Electron Limited, Intel Corporation
    Inventors: Keisuke Suzuki, Toshiyuki Ikeuchi, Kimiya Aoki, David Paul Brunco, Steven Robert Soss, Anthony Dip