Abstract: A method for forming a memory device includes masking a photoresist material using a reticle and a developer having a polarity opposite that of the photoresist to provide an island of photoresist material. A planarizing layer is etched to establish a pillar of planarizing material defined by the island of photoresist material. A metal layer is etched to form a metal pillar having a diameter about the same as the pillar of planarizing material. A memory stack is etched to form a memory stack pillar having a diameter about the same as the metal pillar. A magnetoresistive memory cell includes a magnetic tunnel junction pillar having a circular cross section. The pillar has a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer. A first conductive contact is disposed above the magnetic tunnel junction pillar. A second conductive contact is disposed below the magnetic tunnel junction pillar.

Abstract: A magnetoresistive memory cell includes a magnetic tunnel junction pillar having a circular cross section. The pillar has a pinned magnetic layer, a tunnel barrier layer, and a free magnetic layer. A first conductive contact is disposed above the magnetic tunnel junction pillar. A second conductive contact is disposed below the magnetic tunnel junction pillar.

Abstract: A mechanism is provided for fabricating a thermally assisted magnetoresistive random access memory device. A bottom thermal barrier is formed on a bottom contact. A magnetic tunnel junction is formed on the bottom thermal barrier. The magnetic tunnel junction includes a top ferromagnetic layer formed on a tunnel barrier. The tunnel barrier is formed on a bottom ferromagnetic layer. A top thermal barrier is formed on the top ferromagnetic layer. A top contact is formed on the top thermal barrier. The top contact is reduced to a first diameter. The tunnel barrier and the bottom ferromagnetic layer each have a second diameter. The first diameter of the top contact is smaller than the second diameter.

Abstract: The present invention provides integrated circuit chips having chip identification aspects. The chips include magnetic tunnel junction (MTJ) structures, and more specifically, include permanent bit strings used for chip identification and/or authentication. Systems and processes for chip identification are also disclosed herein. The MTJ element structures provided herein can have a defined resistance profile such that the intrinsic variability of the MTJ element structure is used to encode and generate a bit string that becomes a fingerprint for the chip. In some embodiments, an oxygen treatment covering all or a selected portion of an array of MTJ elements can be used to create a mask or secret key that can be used and implemented to enhance chip identification.

Abstract: Embodiments are directed to a sensor having a first electrode, a second electrode and a detector region electrically coupled between the first electrode region and the second electrode region. The detector region includes a first layer having a topological insulator. The topological insulator includes a conducting path along a surface of the topological insulator, and the detector region further includes a second layer having a first insulating magnetic coupler, wherein a magnetic field applied to the detector region changes a resistance of the conducting path.

Abstract: Embodiments are directed to a sensor having a first electrode, a second electrode and a detector region electrically coupled between the first electrode region and the second electrode region. The detector region includes a first layer having a topological insulator. The topological insulator includes a conducting path along a surface of the topological insulator, and the detector region further includes a second layer having a first insulating magnetic coupler, wherein a magnetic field applied to the detector region changes a resistance of the conducting path.

Abstract: The present invention provides integrated circuit chips having chip identification aspects. The chips include magnetic tunnel junction (MTJ) structures, and more specifically, include permanent bit strings used for chip identification and/or authentication. Systems and processes for chip identification are also disclosed herein. The MTJ element structures provided herein can have a defined resistance profile such that the intrinsic variability of the MTJ element structure is used to encode and generate a bit string that becomes a fingerprint for the chip. In some embodiments, an oxygen treatment covering all or a selected portion of an array of MTJ elements can be used to create a mask or secret key that can be used and implemented to enhance chip identification.

Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.

Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.

Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.

Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a free layer and a reference layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Bottom contacts are separated from one another by a column space while the plurality of bottom contacts are self-aligned to the linear magnetic tunnel junction structure, such that the plurality of bottom contacts are in the line with and underneath the linear magnetic tunnel junction structure. The bottom contacts abut a bottom of the linear magnetic tunnel junction structure. MRAM devices are formed by having non-conducting parts of the free layer isolating individual interfaces between the bottom contacts and the free layer. The MRAM devices are formed in the line of the linear magnetic tunnel junction structure.

Abstract: A technique relates to an MRAM system. A conformal film covers trenches formed in an upper material. The upper material covers conductive islands in a substrate. The conformal film is selectively etched to leave sidewalls on the trenches. The sidewalls are etched into vertical columns self-aligned to and directly on top of the conductive islands below. A filling material is deposited and planarized to leave exposed tops of the vertical columns. An MTJ element is formed on top of the filling material and exposed tops of the vertical columns. The MTJ element is patterned into lines corresponding to the vertical columns, and each of the lines has a line MTJ element self-aligned to one of the vertical columns. Line MRAM devices are formed by patterning the MTJ element into the lines. Each of line MRAM devices respectively include the line MTJ element self-aligned to the one of the vertical columns.

Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a reference layer and a free layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Magnetoresistive random access memory (MRAM) devices are formed of the reference layer, the non-magnetic tunnel barrier, and the free layer, each of the MRAM devices are in the line. Self-aligned contacts are formed on top of the linear magnetic tunnel junction structure, and the self-aligned contacts individually define the MRAM devices. The self-aligned contacts are separated from one another in the line. Bottom conductive vias are underneath the linear magnetic tunnel junction structure. The bottom conductive vias abut the reference layer of the linear magnetic tunnel junction structure.

Abstract: Magnetic tunnel junction antifuse devices are protected from degradation caused by programming voltage drop across the gates of unselected magnetic tunnel junction antifuses by connecting said magnetic tunnel junction serially with a first field effect transistor and a second field effect transistor, the first field effect transistor having its gate connected to a positive supply voltage while the gate of the second field effect transistor is switchably connected to a programming voltage.

Abstract: A technique relates to an MRAM system. A conformal film covers trenches formed in an upper material. The upper material covers conductive islands in a substrate. The conformal film is selectively etched to leave sidewalls on the trenches. The sidewalls are etched into vertical columns self-aligned to and directly on top of the conductive islands below. A filling material is deposited and planarized to leave exposed tops of the vertical columns. An MTJ element is formed on top of the filling material and exposed tops of the vertical columns. The MTJ element is patterned into lines corresponding to the vertical columns, and each of the lines has a line MTJ element self-aligned to one of the vertical columns. Line MRAM devices are formed by patterning the MTJ element into the lines. Each of line MRAM devices respectively include the line MTJ element self-aligned to the one of the vertical columns.

Abstract: A technique relates to a linear magnetoresistive random access memory (MRAM) device. A linear magnetic tunnel junction structure includes a non-magnetic tunnel barrier on top of a reference layer and a free layer on top of the non-magnetic tunnel barrier, where the linear magnetic tunnel junction structure is in a line. Magnetoresistive random access memory (MRAM) devices are formed of the reference layer, the non-magnetic tunnel barrier, and the free layer, each of the MRAM devices are in the line. Self-aligned contacts are formed on top of the linear magnetic tunnel junction structure, and the self-aligned contacts individually define the MRAM devices. The self-aligned contacts are separated from one another in the line. Bottom conductive vias are underneath the linear magnetic tunnel junction structure. The bottom conductive vias abut the reference layer of the linear magnetic tunnel junction structure.

Abstract: A method of making a magnetic random access memory (MRAM) device comprising forming a magnetic tunnel junction on an electrode, the magnetic tunnel junction comprising a first reference layer, a free layer, and a first tunnel barrier layer; and depositing an encapsulating silicon nitride film on and along sidewalls of the magnetic tunnel junction; wherein the silicon nitride film has a N:Si ratio from 0.1 to 1. An MRAM device made by the above method is also disclosed.

Abstract: A mechanism is provided for fabricating a thermally assisted magnetoresistive random access memory device. A bottom thermal barrier is formed on a bottom contact. A magnetic tunnel junction is formed on the bottom thermal barrier. The magnetic tunnel junction includes a top ferromagnetic layer formed on a tunnel barrier. The tunnel barrier is formed on a bottom ferromagnetic layer. A top thermal barrier is formed on the top ferromagnetic layer. A top contact is formed on the top thermal barrier. The top contact is reduced to a first diameter. The tunnel barrier and the bottom ferromagnetic layer each have a second diameter. The first diameter of the top contact is smaller than the second diameter.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.