Abstract: A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). A storage layer has an anisotropic axis, in which the storage layer is configured to store a state in off axis positions and on axis positions. The off axis positions are not aligned with the anisotropic axis. A tunnel barrier is disposed on top of the storage layer. A ferromagnetic sense layer is disposed on top of the tunnel barrier.

Abstract: A mechanism is provided for fabricating a thermally assisted magnetoresistive random access memory device. A bottom thermal barrier is formed on a bottom contact. A magnetic tunnel junction is formed on the bottom thermal barrier. The magnetic tunnel junction includes a top ferromagnetic layer formed on a tunnel barrier. The tunnel barrier is formed on a bottom ferromagnetic layer. A top thermal barrier is formed on the top ferromagnetic layer. A top contact is formed on the top thermal barrier. The top contact is reduced to a first diameter. The tunnel barrier and the bottom ferromagnetic layer each have a second diameter. The first diameter of the top contact is smaller than the second diameter.

Abstract: A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). A non-magnetic heating structure is formed of a barrier seed layer disposed on a buffer layer. A non-magnetic tunnel barrier is disposed on the barrier seed layer. A barrier cap layer is disposed on the non-magnetic tunnel barrier. A top buffer layer is disposed on the barrier cap layer. An antiferromagnetic layer is disposed on the top buffer layer of the non-magnetic heating structure. A magnetic tunnel junction is disposed on the antiferromagnetic layer. The magnetic tunnel junction includes a ferromagnetic storage layer disposed on the antiferromagnetic layer, a non-magnetic active tunnel barrier disposed on the ferromagnetic storage layer, and a ferromagnetic sense layer disposed on the non-magnetic active tunnel barrier.

Abstract: A magnetoresistive memory cell includes a magnetoresistive tunnel junction stack and a dielectric encapsulation layer covering sidewall portions of the stack and being opened over a top of the stack. A conductor is formed in contact with a top portion of the stack and covering the encapsulation layer. A magnetic liner encapsulates the conductor and is gapped apart from the encapsulating layer covering the sidewall portions of the stack.

Abstract: A racetrack memory cell device include a dielectric, an electrode disposed in the dielectric, a metal strap disposed in the dielectric, a nanowire disposed in the dielectric between the electrode and the metal strap and a magnetic tunnel junction disposed in the dielectric on the metal strap, and axially with the nanowire.

Abstract: A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap.

Abstract: A technique is provided for a thermally assisted magnetoresistive random access memory device. A magnetic tunnel junction is formed. Contact wiring having a top contact electrode and a bottom contact electrode is formed. The contact wiring provides write bias to heat the magnetic tunnel junction. A multilayer dielectric encapsulant is configured to retain the heat within the magnetic tunnel junction.

Abstract: Embodiments are directed to injecting domain walls in a magnetic racetrack memory. In some embodiments, a racetrack comprising a nanowire is coupled with a gate in order to manipulate an anisotropy associated with the nanowire. The racetrack and gate is coupled with a pinning layer configured to establish a magnetization direction in the nanowire.

Abstract: A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM) with reduced power for reading and writing. A tunnel barrier is disposed adjacent to a ferromagnetic sense layer and a ferromagnetic storage layer, such that the tunnel barrier is sandwiched between the ferromagnetic sense layer and the ferromagnetic storage layer. An antiferromagnetic pinning layer is disposed adjacent to the ferromagnetic storage layer. The pinning layer pins a magnetic moment of the storage layer until heating is applied. The storage layer includes a non-magnetic material to reduce a storage layer magnetization as compared to not having the non-magnetic material. The sense layer includes the non-magnetic material to reduce a sense layer magnetization as compared to not having the non-magnetic material.

Abstract: A technique is provided for a thermally assisted magnetoresistive random access memory device. The device has a synthetic antiferromagnetic layer disposed on an antiferromagnetic layer. The synthetic antiferromagnetic layer has a first ferromagnetic storage layer, a non-magnetic coupling layer disposed on the first ferromagnetic storage layer, and a second ferromagnetic storage layer disposed on the non-magnetic coupling layer. A non-magnetic tunnel barrier is disposed on the second ferromagnetic storage layer, and a ferromagnetic sense layer is disposed on the non-magnetic tunnel barrier. A first ferromagnetic critical temperature of the first ferromagnetic storage layer is higher than an antiferromagnetic critical temperature of the antiferromagnetic layer, is higher than a second ferromagnetic critical temperature of the second ferromagnetic storage layer, and is higher than a third ferromagnetic critical temperature of the ferromagnetic sense layer.

Abstract: A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance.

Abstract: A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, the selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance.

Abstract: A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap.

Abstract: A technique is provided for a thermally assisted magnetoresistive random access memory device. The device has a synthetic antiferromagnetic layer disposed on an antiferromagnetic layer. The synthetic antiferromagnetic layer has a first ferromagnetic storage layer, a non-magnetic coupling layer disposed on the first ferromagnetic storage layer, and a second ferromagnetic storage layer disposed on the non-magnetic coupling layer. A non-magnetic tunnel barrier is disposed on the second ferromagnetic storage layer, and a ferromagnetic sense layer is disposed on the non-magnetic tunnel barrier. A first ferromagnetic critical temperature of the first ferromagnetic storage layer is higher than an antiferromagnetic critical temperature of the antiferromagnetic layer, is higher than a second ferromagnetic critical temperature of the second ferromagnetic storage layer, and is higher than a third ferromagnetic critical temperature of the ferromagnetic sense layer.

Abstract: A technique is provided for a thermally assisted magnetoresistive random access memory device. A magnetic tunnel junction is formed. Contact wiring having a top contact electrode and a bottom contact electrode is formed. The contact wiring provides write bias to heat the magnetic tunnel junction. A multilayer dielectric encapsulant is configured to retain the heat within the magnetic tunnel junction.

Abstract: A technique is provided for a thermally assisted magnetoresistive random access memory device. A magnetic tunnel junction is formed. Contact wiring having a top contact electrode and a bottom contact electrode is formed. The contact wiring provides write bias to heat the magnetic tunnel junction. A multilayer dielectric encapsulant is configured to retain the heat within the magnetic tunnel junction.

Abstract: A method of pinning magnetic domain walls in magnetic domain shift registers includes pinning the magnetic domain walls at a plurality of pinning sites in a nanowire, reducing an energy of the pinning of the magnetic domain walls and shifting the magnetic domain walls in the nanowire by applying a shift current in a control wire adjacent the nanowire.

Abstract: A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). The device includes a magnetic tunnel junction configured to store data, a first multilayer contact structure positioned on one end of the magnetic tunnel junction, and a second multilayer contact structure positioned on an opposite end of the magnetic tunnel junction. The first multilayer contact structure and the second multilayer contact structure each include multiple layers of metals. The multiple layers of metals are structured to inhibit thermal conductivity between the magnetic tunnel junction and surrounding structures, and the multiple layers of metals are structured to electrically conduct electrical current.

Abstract: A thermally assisted magnetoresistive random access memory cell, a corresponding array, and a method for fabricating the array. An example cell includes a first metal layer, a second metal layer, an interlayer, a first magnetic stack, and a first non-magnetic via. The first metal layer includes a pad and a first metal line, with the pad not in direct contact with the first metal line. The second metal layer includes a second metal line and a metal strap. The second metal line is perpendicular to the first metal line and not in contact with the metal strap. The interlayer is located between the first and second metal layers. The first metal line is not in direct contact with the interlayer. The first magnetic stack is in direct contact with the interlayer and the metal strap. The first non-magnetic via is in direct contact with the pad and the metal strap.

Abstract: Embodiments are directed to injecting domain walls in a magnetic racetrack memory. In some embodiments, a racetrack comprising a nanowire is coupled with a gate in order to manipulate an anisotropy associated with the nanowire. The racetrack and gate is coupled with a pinning layer configured to establish a magnetization direction in the nanowire.