Abstract: A method of making a magnetic random access memory (MRAM) device includes depositing a spacer material on an electrode; forming a magnetic tunnel junction (MTJ) on the spacer material that includes a reference layer in contact with the spacer material, a free layer, and a tunnel barrier layer; patterning a hard mask on the free layer; etching the MTJ and the spacer material to transfer a pattern of the hard mask into the MTJ and the spacer material; forming an insulating layer along a sidewall of the hard mask, the MTJ, and the spacer material; disposing an interlayer dielectric (ILD) on and around the hard mask, MTJ, and spacer material; etching through the ILD to form a trench that extends to a surface and sidewall of the hard mask and a sidewall of a portion of the MTJ; and disposing a metal in the trench to form a contact electrode.

Abstract: A magnetoresistive memory cell includes a magnetoresistive tunnel junction stack and a dielectric encapsulation layer covering sidewall portions of the stack and being opened over a top of the stack. A conductor is formed in contact with a top portion of the stack and covering the encapsulation layer. A magnetic liner encapsulates the conductor and is gapped apart from the encapsulating layer covering the sidewall portions of the stack.

Abstract: A magnetoresistive memory cell includes a magnetoresistive tunnel junction stack and a dielectric encapsulation layer covering sidewall portions of the stack and being opened over a top of the stack. A conductor is formed in contact with a top portion of the stack and covering the encapsulation layer. A magnetic liner encapsulates the conductor and is gapped apart from the encapsulating layer covering the sidewall portions of the stack.

Abstract: The present invention provides integrated circuit chips having chip identification aspects. The chips include magnetic tunnel junction (MTJ) structures, and more specifically, include permanent bit strings used for chip identification and/or authentication. Systems and processes for chip identification are also disclosed herein. The MTJ element structures provided herein can have a defined resistance profile such that the intrinsic variability of the MTJ element structure is used to encode and generate a bit string that becomes a fingerprint for the chip. In some embodiments, an oxygen treatment covering all or a selected portion of an array of MTJ elements can be used to create a mask or secret key that can be used and implemented to enhance chip identification.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.

Abstract: A magnetoresistive memory cell includes a magnetoresistive tunnel junction stack and a dielectric encapsulation layer covering sidewall portions of the stack and being opened over a top of the stack. A conductor is formed in contact with a top portion of the stack and covering the encapsulation layer. A magnetic liner encapsulates the conductor and is gapped apart from the encapsulating layer covering the sidewall portions of the stack.

Abstract: A method of making a magnetic random access memory (MRAM) device includes depositing a spacer material on an electrode; forming a magnetic tunnel junction (MTJ) on the spacer material that includes a reference layer in contact with the spacer material, a free layer, and a tunnel barrier layer; patterning a hard mask on the free layer; etching the MTJ and the spacer material to transfer a pattern of the hard mask into the MTJ and the spacer material; forming an insulating layer along a sidewall of the hard mask, the MTJ, and the spacer material; disposing an interlayer dielectric (ILD) on and around the hard mask, MTJ, and spacer material; etching through the ILD to form a trench that extends to a surface and sidewall of the hard mask and a sidewall of a portion of the MTJ; and disposing a metal in the trench to form a contact electrode.

Abstract: A method of magnetic tunnel junction patterning for magnetoresisitive random access memory devices using low atomic weight ion sputtering. The method includes: providing a magnetoresistive random access memory device including a hard mask metal, a MTJ element, and a semiconductor substrate, wherein the hard mask metal is disposed on the MTJ element and, wherein the MTJ element is disposed on the semiconductor substrate; and etching back the MTJ element into a plurality of MTJ element pillars using a low atomic weight ion sputtering. A magnetoresistive random access memory device using low atomic weight ion sputtering. The device includes: a semiconductor substrate; a plurality of MTJ element pillars disposed on the semiconductor substrate, wherein the plurality of MTJ element pillars is etched from a MTJ element using a low atomic weight ion sputtering; and a hard mask metal disposed on the MTJ element pillars.

Abstract: A method of magnetic tunnel junction patterning for magnetoresisitive random access memory devices using low atomic weight ion sputtering. The method includes: providing a magnetoresistive random access memory device including a hard mask metal, a MTJ element, and a semiconductor substrate, wherein the hard mask metal is disposed on the MTJ element and, wherein the MTJ element is disposed on the semiconductor substrate; and etching back the MTJ element into a plurality of MTJ element pillars using a low atomic weight ion sputtering. A magnetoresistive random access memory device using low atomic weight ion sputtering. The device includes: a semiconductor substrate; a plurality of MTJ element pillars disposed on the semiconductor substrate, wherein the plurality of MTJ element pillars is etched from a MTJ element using a low atomic weight ion sputtering; and a hard mask metal disposed on the MTJ element pillars.

Abstract: A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM) with reduced power for reading and writing. A tunnel barrier is disposed adjacent to a ferromagnetic sense layer and a ferromagnetic storage layer, such that the tunnel barrier is sandwiched between the ferromagnetic sense layer and the ferromagnetic storage layer. An antiferromagnetic pinning layer is disposed adjacent to the ferromagnetic storage layer. The pinning layer pins a magnetic moment of the storage layer until heating is applied. The storage layer includes a non-magnetic material to reduce a storage layer magnetization as compared to not having the non-magnetic material. The sense layer includes the non-magnetic material to reduce a sense layer magnetization as compared to not having the non-magnetic material.

Abstract: A technique relates to a semiconductor device. First metal contacts are formed on top of a substrate. The first metal contacts are arranged in a first direction, and the first metal contacts are arranged such that areas of the substrate remain exposed. Insulator pads are positioned at predefined locations on top of the first metal contacts, such that the insulator pads are spaced from one another. Second metal contacts are formed on top of the insulator pads, such that the second metal contacts are arranged in a second direction different from the first direction. The first and second metal contacts sandwich the insulator pads at the predefined locations. Surface-sensitive conductive channels are formed to contact the first metal contacts and the second metal contacts. Four-terminal devices are defined by the surface-sensitive conductive channels contacting a pair of the first metal contacts and contacting a pair of the metal contacts.

Abstract: A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). A storage layer has an anisotropic axis, in which the storage layer is configured to store a state in off axis positions and on axis positions. The off axis positions are not aligned with the anisotropic axis. A tunnel barrier is disposed on top of the storage layer. A ferromagnetic sense layer is disposed on top of the tunnel barrier.

Abstract: According to an embodiment of the invention, a method of making a magnetic random access memory device includes: forming a magnetic tunnel junction on an electrode, the magnetic tunnel junction comprising a reference layer positioned in contact with the electrode, a tunnel barrier layer arranged on the reference layer, and a free layer arranged on the tunnel barrier layer; depositing an encapsulating layer on and along sidewalls of the magnetic tunnel junction; depositing an interlayer dielectric layer on the encapsulating layer disposed on the magnetic tunnel junction; annealing the magnetic tunnel junction; and implanting hydrogen in a portion of the magnetic tunnel junction. According to another embodiment of the invention, implanting of hydrogen in a portion of the magnetic tunnel junction occurs after forming a magnetic tunnel junction trench. An MRAM device with hydrogen atoms incorporated in a portion of the magnetic tunnel junction is also disclosed.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A substrate is provided. A plurality of metal portions are formed on the substrate, wherein the plurality of metal portions are arranged such that areas of the substrate remain exposed. A thin film layer is deposited on the plurality of metal portions and the exposed areas of the substrate. A dielectric layer is deposited, wherein the dielectric layer is in contact with portions of the thin film layer on the plurality of metal portions, and wherein the dielectric layer is not in contact with portions of the thin film layer on the exposed areas of the substrate such that one or more enclosed spaces are present between the thin film layer on the exposed areas of the substrate and the dielectric layer.

Abstract: A thermally assisted magnetoresistive random access memory (TAS-MRAM) device includes a magnetic tunnel junction interposed between a first electrical contact and a second electrical contact. The TAS-MRAM device further includes a dielectric layer that is formed on an upper surface of the first electrical contact and that encapsulates the second electrical contact. The dialectic layer has at least one vacuum cavity between an adjacent outer wall of the magnetic tunnel junction and the dielectric layer.

Abstract: A technique relates to an MRAM system. A conformal film covers trenches formed in an upper material. The upper material covers conductive islands in a substrate. The conformal film is selectively etched to leave sidewalls on the trenches. The sidewalls are etched into vertical columns self-aligned to and directly on top of the conductive islands below. A filling material is deposited and planarized to leave exposed tops of the vertical columns. An MTJ element is formed on top of the filling material and exposed tops of the vertical columns. The MTJ element is patterned into lines corresponding to the vertical columns, and each of the lines has a line MTJ element self-aligned to one of the vertical columns. Line MRAM devices are formed by patterning the MTJ element into the lines. Each of line MRAM devices respectively include the line MTJ element self-aligned to the one of the vertical columns.

Abstract: A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). A storage layer has an anisotropic axis, in which the storage layer is configured to store a state in off axis positions and on axis positions. The off axis positions are not aligned with the anisotropic axis. A tunnel barrier is disposed on top of the storage layer. A ferromagnetic sense layer is disposed on top of the tunnel barrier.

Abstract: A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). A storage layer has an anisotropic axis, in which the storage layer is configured to store a state in off axis positions and on axis positions. The off axis positions are not aligned with the anisotropic axis. A tunnel barrier is disposed on top of the storage layer. A ferromagnetic sense layer is disposed on top of the tunnel barrier.

Abstract: A mechanism is provided for a thermally assisted magnetoresistive random access memory device (TAS-MRAM). A non-magnetic heating structure is formed of a barrier seed layer disposed on a buffer layer. A non-magnetic tunnel barrier is disposed on the barrier seed layer. A barrier cap layer is disposed on the non-magnetic tunnel barrier. A top buffer layer is disposed on the barrier cap layer. An antiferromagnetic layer is disposed on the top buffer layer of the non-magnetic heating structure. A magnetic tunnel junction is disposed on the antiferromagnetic layer. The magnetic tunnel junction includes a ferromagnetic storage layer disposed on the antiferromagnetic layer, a non-magnetic active tunnel barrier disposed on the ferromagnetic storage layer, and a ferromagnetic sense layer disposed on the non-magnetic active tunnel barrier.

Abstract: A racetrack memory cell device include a dielectric, an electrode disposed in the dielectric, a metal strap disposed in the dielectric, a nanowire disposed in the dielectric between the electrode and the metal strap and a magnetic tunnel junction disposed in the dielectric on the metal strap, and axially with the nanowire.