Patents by Inventor Anthony Yen

Anthony Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10001701
    Abstract: A structure including an EUV mask and a pellicle attached to the EUV mask. The pellicle includes a pellicle frame and a plurality of pellicle membrane layers attached to the pellicle frame. The plurality of pellicle membrane layers include at least one core pellicle membrane layer and an additional pellicle membrane layer is disposed on the at least one core pellicle membrane layer. In some embodiments, the additional pellicle membrane layer is a material having a thermal emissivity greater than 0.2, a transmittance greater than 80%, and a refractive index (n) for 13.5 nanometer source of greater than 0.9.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pei-Cheng Hsu, Hsin-Chang Lee, Yun-Yue Lin, Hsuan-Chen Chen, Hsuan-I Wang, Anthony Yen
  • Patent number: 9996013
    Abstract: An extreme ultraviolet lithography (EUVL) system is disclosed. The system includes an extreme ultraviolet (EUV) mask with three states having respective reflection coefficient is r1, r2 and r3, wherein r3 is a pre-specified value that is a function of r1 and r2. The system also includes a nearly on-axis illumination (ONI) with partial coherence ? less than 0.3 to expose the EUV mask to produce diffracted light and non-diffracted light. The system further includes a projection optics box (PUB) to remove a portion of the non-diffracted light and to collect and direct the diffracted light and the remaining non-diffracted light to expose a target.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: June 12, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
  • Patent number: 9995999
    Abstract: A lithography mask includes a substrate, a reflective multilayer (ML) on the substrate, and a barrier layer on the reflective ML. The barrier layer includes at least one material selected from the group consisting of ruthenium nitride, hafnium oxide, aluminum nitride, boron carbide, boron nitride, and a combination thereof.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yun-Yue Lin, Hsin-Chang Lee, Chia-Jen Chen, Anthony Yen
  • Publication number: 20180149959
    Abstract: A lithography mask includes a substrate that contains a low thermal expansion material (LTEM). A reflective structure is disposed over a first side of the substrate. An absorber layer is disposed over the reflective structure. The absorber layer contains one or more first overlay marks. A conductive layer is disposed over a second side of the substrate, the second side being opposite the first side. The conductive layer contains portions of one or more second overlay marks. In some embodiments, the lithography mask includes an EUV lithography mask.
    Type: Application
    Filed: August 7, 2017
    Publication date: May 31, 2018
    Inventors: Yun-Yue Lin, Hsin-Chang Lee, Chia-Jen Chen, Chih-Cheng Lin, Anthony Yen, Chin-Hsiang Lin
  • Patent number: 9964850
    Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes loading a mask to a lithography system, wherein the mask includes an one-dimensional integrated circuit (1D IC) pattern; utilizing a pupil phase modulator in the lithography system to modulate phase of light diffracted from the mask; and performing a lithography exposing process to a target in the lithography system with the mask and the pupil phase modulator.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: May 8, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Cheng Lu, Chia-Hao Hsu, Shinn-Sheng Yu, Chia-Chen Chen, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9897910
    Abstract: A method for forming a lithography mask includes forming a capping layer on a reflective multilayer layer, the capping layer comprising a first material, forming a patterned patterning layer on the capping layer, and introducing a secondary material into the capping layer, the secondary material having an atomic number that is smaller than 15.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: February 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Pei-Cheng Hsu, Chih-Cheng Lin, Ta-Cheng Lien, Wei-Shiuan Chen, Hsin-Chang Lee, Anthony Yen
  • Patent number: 9886543
    Abstract: A pattern of features of an integrated circuit is provided. A configuration of a pupil of an extreme ultraviolet wavelength radiation beam (also referred to as an illumination mode), is selected. The selected configuration is an asymmetric, single pole configuration. At least one disparity is determined between a simulated imaging using the selected configuration and a designed imaging for the pattern of features. A parameter (also referred to as a compensation parameter) is then modified to address the at least one disparity, wherein the parameter at least one a design feature, a mask feature, and a lithography process parameter. A substrate is then exposed to the pattern of features using the selected configuration and the modified parameter.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chun Chung, Norman Chen, Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
  • Patent number: 9869939
    Abstract: A method for being used in a lithography process is provided. The method includes receiving a first mask, a second mask and a substrate with a set of baseline registration marks. A first set of registration marks is formed on the substrate using the first mask and a first exposure tool, and a first set of overlay errors is determined. The first set of registration marks is removed and a second set of registration marks is formed on the substrate using the second mask and a second exposure tool. A second set of overlay errors is determined. A set of tool-induced overlay errors is generated from the first and second sets of overlay errors and used in fabricating a third mask. The third mask can then be used in the lithography process to accommodate the overlay errors caused by different exposure tools, different masks, and different mask writers.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shinn-Sheng Yu, Anthony Yen
  • Patent number: 9869928
    Abstract: Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A planarized process is provided to remove the absorber layer above the top surface of the hard mask layer and form an absorber in the opening, wherein the absorber has a top portion wider than a bottom portion.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tao-Min Huang, Chih-Tsung Shih, Chia-Jen Chen, Hsin-Chang Lee, Anthony Yen
  • Patent number: 9870612
    Abstract: A method includes inspecting a mask to locate a defect region for a defect of the mask. A phase distribution of an aerial image of the defect region is acquired. A point spread function of an imaging system is determined. One or more repair regions of the mask are identified based on the phase distribution of the aerial image of the defect region and the point spread function. A repair process is performed to the one or more repair regions of the mask to form one or more repair features.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shinn-Sheng Yu, Anthony Yen, Wen-Chuan Wang, Sheng-Chi Chin
  • Publication number: 20170352144
    Abstract: A method includes inspecting a mask to locate a defect region for a defect of the mask. A phase distribution of an aerial image of the defect region is acquired. A point spread function of an imaging system is determined. One or more repair regions of the mask are identified based on the phase distribution of the aerial image of the defect region and the point spread function. A repair process is performed to the one or more repair regions of the mask to form one or more repair features.
    Type: Application
    Filed: September 1, 2016
    Publication date: December 7, 2017
    Inventors: Shinn-Sheng YU, Anthony YEN, Wen-Chuan WANG, Sheng-Chi CHIN
  • Publication number: 20170343892
    Abstract: The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.
    Type: Application
    Filed: August 16, 2017
    Publication date: November 30, 2017
    Inventors: Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
  • Patent number: 9829785
    Abstract: An extreme ultraviolet lithography (EUVL) system for patterning a semiconductor wafer includes an extreme ultraviolet (EUV) mask. The EUV mask includes first and second states, and further includes a polygon region and an open-spacing region. The polygon region includes a plurality of main polygons separated by a plurality of first fields. The open-spacing region is located outside the polygon region, and includes a plurality of sub-resolution polygon and second fields, and does not include any main polygons. The system also includes a nearly on-axis illumination (ONI) to expose the EUV mask and optics to direct diffracted lights reflected from the EUV mask towards the semiconductor wafer.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: November 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Publication number: 20170338103
    Abstract: A method includes patterning a resist layer formed over a substrate, resulting in a resist pattern; and transferring the resist pattern to an anti-reflection coating (ARC) layer formed under the resist layer and over the substrate, resulting in a patterned ARC layer. The method further includes treating the patterned ARC layer with an ion beam, resulting in a treated patterned ARC layer, wherein the ion beam is generated with a first gas and is directed towards the patterned ARC layer at a tilt angle at least 10 degrees. The method further includes etching the substrate with the treated patterned ARC layer as an etch mask.
    Type: Application
    Filed: August 9, 2017
    Publication date: November 23, 2017
    Inventors: Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9823585
    Abstract: Systems and methods for monitoring the focus of an EUV lithography system are disclosed. Another aspect includes a method having operations of measuring a first shift value for a first patterned set of sub-structures of a focus test structure on a wafer and measuring a second shift value for a second patterned set of sub-structures of the test structure on the wafer. The test structure may be formed on the wafer using asymmetric illumination, with the first patterned set of sub-structures having a first pitch and the second patterned set of sub-structures having a second pitch that is different from the first pitch. The method may further include determining a focus shift compensation for an illumination system based on a difference between the first shift value and the second shift value.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: November 21, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Tsung Shih, Chieh-Jen Cheng, Jeng-Horng Chen, Chia-Chen Chen, Shinn-Sheng Yu, Anthony Yen, Wei-Chih Lai
  • Publication number: 20170277040
    Abstract: Lithography methods and corresponding lithography apparatuses are disclosed herein for improving throughput of lithography exposure processes. An exemplary lithography method includes generating a plurality of target material droplets and generating radiation from the plurality of target material droplets based on a dose margin to expose a wafer. The dose margin indicates how many of the plurality of target material droplets are reserved for dose control. In some implementations, the plurality of target material droplets are grouped into a plurality of bursts, and the lithography method further includes performing an inter-compensation operation that designates an excitation state of target material droplets in one of the plurality of bursts to compensate for an energy characteristic of another one of the plurality of bursts.
    Type: Application
    Filed: June 8, 2017
    Publication date: September 28, 2017
    Inventors: Yen-Cheng Lu, Jeng-Horng Chen, Shun-Der Wu, Anthony Yen
  • Patent number: 9766536
    Abstract: The present disclosure provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A multilayer (ML) structure is disposed over the substrate. The ML structure is configured to reflect radiation. The ML structure contains a plurality of interleaving film pairs. Each film pair includes a first film and a second film. The first film and the second film have different material compositions. Each film pair has a respective thickness. For at least a subset of the plurality of the film pairs, the respective thicknesses of the film pairs change randomly along a predefined direction.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: September 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
  • Patent number: 9760015
    Abstract: A process of an extreme ultraviolet lithography is disclosed. The process includes receiving an extreme ultraviolet (EUV) mask, an EUV radiation source and an illuminator. The process also includes exposing the EUV mask by a radiation, originating from the EUV radiation source and directed by the illuminator, with a less-than-three-degree chief ray angle of incidence at the object side (CRAO). The process further includes removing most of the non-diffracted light and collecting and directing the diffracted light and the not removed non-diffracted light by a projection optics box (POB) to expose a target.
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: September 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shinn-Sheng Yu, Anthony Yen, Yen-Cheng Lu
  • Patent number: 9748133
    Abstract: A method includes defining a metal pattern layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is grown over the metal pattern layer and the first dielectric layer. A metal trench is formed with a metal width in the first dielectric layer. A via hole is formed with a via width in the second dielectric layer.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: August 29, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Patent number: 9733562
    Abstract: An apparatus comprises a low EUV reflectivity (LEUVR) mask. The LEUVR mask includes a low thermal expansion material (LTEM) layer; a reflective multilayer (ML) over the LTEM layer; and a patterned absorption layer over the reflective ML. The reflective ML has less than 2% EUV reflectivity.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: August 15, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen