Patents by Inventor Anthony Yen

Anthony Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Lithography system and method for patterning photoresist layer on EUV mask
    Patent number: 9341937
    Abstract: A lithography system for an extreme ultra violet (EUV) mask is provided. The lithography system includes a coupling module. The coupling module includes at least one mask contact element configured to touch a peripheral area of the EUV mask. The lithography system also includes an ammeter having an end electrically connected to the EUV mask through the at least one mask contact element and another end connected to a ground potential. The ammeter includes a sensor configured to measure a current conducting from the EUV mask to the ground potential and a compensation circuit configured to provide a compensation current that is opposite to the current measured by the sensor.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: May 17, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Yun-Yue Lin, Chia-Jen Chen, Hsin-Chang Lee, Anthony Yen
  • EUV MASK WITH ITO ABSORBER TO SUPPRESS OUT OF BAND RADIATION
    Publication number: 20160124297
    Abstract: The present disclosure also provides a photolithography mask. The photolithography mask includes a substrate that contains a low thermal expansion material (LTEM). A reflective structure is disposed over the substrate. A capping layer is disposed over the reflective structure. An absorber layer is disposed over the capping layer. The absorber layer contains an indium tin oxide (ITO) material. In some embodiments, the ITO material has a SnO6 crystalline structure.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 5, 2016
    Inventors: Yi-Ling Hsieh, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • METHOD OF MAKING AN EXTREME ULTRAVIOLET PELLICLE
    Publication number: 20160109798
    Abstract: The present disclosure relates to a method of forming an extreme ultraviolet (EUV) pellicle having an pellicle film connected to a pellicle frame without a supportive mesh, and an associated apparatus. In some embodiments, the method is performed by forming a cleaving plane within a substrate. A pellicle frame is attached to an upper surface of the substrate, and the substrate is cleaved along the cleaving plane to form a pellicle film attached to the pellicle frame. The method forms the pellicle without using a support structure, which may block EUV radiation and cause substantial non-uniformities in the intensity of EUV radiation incident on an EUV reticle.
    Type: Application
    Filed: December 28, 2015
    Publication date: April 21, 2016
    Inventors: Chih-Tsung Shih, Tien-Hsi Lee, Chia-Jen Chen, Shang-Chieh Chien, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Extreme ultraviolet lithography process and mask
    Patent number: 9316900
    Abstract: A system of an extreme ultraviolet lithography (EUVL) is disclosed. The system includes a mask having first and second reflective regions. The system also includes an illumination to expose the mask to produce a resultant reflected light form the mask. The resultant reflected light is constructed by a first reflected light reflected from the first reflective region and a second reflected light reflected from the second reflective region. The resultant reflected light contains mainly diffracted light. The system also includes a projection optics box (POB) to collect and direct resultant reflected light to expose a target.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: April 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Extreme ultraviolet light (EUV) photomasks, and fabrication methods thereof
    Patent number: 9310675
    Abstract: Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A planarized process is provided to remove the absorber layer above the top surface of the hard mask layer and form an absorber in the opening, wherein the absorber has a top portion wider than a bottom portion.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tao-Min Huang, Chih-Tsung Shih, Chia-Jen Chen, Hsin-Chang Lee, Anthony Yen
  • Extreme ultraviolet lithography process and mask
    Patent number: 9304390
    Abstract: A system and process of an extreme ultraviolet lithography (EUVL) is disclosed. The system and process includes receiving a mask with two states, which have 180 degree phase difference to each other. These different states are assigned to adjacent main polygons and adjacent assist polygons of the mask. A nearly on-axis illumination (ONI) with partial coherence ? less than 0.3 is utilized to expose the mask to produce diffracted lights and non-diffracted lights. A majority portion of the non-diffracted lights and diffracted light with diffraction order higher than 1 are removed. Diffracted light having +1-st and ?1-st diffracted order are collected and directed by a projection optics box (POB) to expose a target.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Mask for use in lithography
    Patent number: 9285671
    Abstract: A mask, or photomask, is used in lithography systems and processes. The mask includes a first polygon of a first state and a second polygon of a second state. The mask also includes a field of the first state and a third polygon of the second state, and in the field. The first and second states are different, and the first and second polygons are located outside of the field.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Anthony Yen
  • Assist feature for a photolithographic process
    Patent number: 9285673
    Abstract: A photomask having a partial-thickness assist feature and a technique for manufacturing the photomask are disclosed. In an exemplary embodiment, the photomask includes a mask substrate, a reflective structure disposed on the mask substrate, and an absorptive layer formed on the reflective structure. A printing feature region and an assist feature region are defined on the mask. The absorptive layer has a first thickness in the printing feature region and a second thickness in the assist feature region that is different from the first thickness. In some such embodiments, the second thickness is configured such that radiation reflected by the assist feature region does not exceed an exposure threshold of a photoresist of a target.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tao-Min Huang, Chia-Jen Chen, Hsin-Chang Lee, Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Method of fabricating mask
    Patent number: 9280046
    Abstract: A method for fabricating an extreme ultraviolet (EUV) mask includes providing a low thermal expansion material (LTEM) layer. A reflective multiple-layer (ML) is deposited over the LTEM layer. A flowable-photosensitive-absorption-layer (FPhAL) is spin coated over the reflective ML. The FPhAL is patterned by a lithography process to form a patterned absorption layer.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Anthony Yen, Chih-Tsung Shih, Ming-Jiun Yao, Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Hsin-Chang Lee
  • Method for Integrated Circuit Patterning
    Publication number: 20160064239
    Abstract: Provided is a method of patterning a substrate. The method includes patterning a resist layer formed over the substrate to result in a resist pattern and treating the resist pattern with an ion beam. The ion beam is generated with a gas, such as CH4, SiH4, Ar, or He; and is directed towards the resist pattern at a tilt angle at least 10 degrees. In embodiments, the ion beam is directed towards the resist pattern at a uniform twist angle, or at a twist angle having a unimodal or bimodal distribution. The ion beam reduces line edge roughness (LER), line width roughness (LWR), and/or critical dimension of the resist pattern. The method further includes etching the substrate with the treated resist pattern as an etch mask.
    Type: Application
    Filed: March 11, 2015
    Publication date: March 3, 2016
    Inventors: Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • SYSTEM AND METHOD FOR PERFORMING LITHOGRAPHY PROCESS IN SEMICONDUCTOR DEVICE FABRICATION
    Publication number: 20160054664
    Abstract: Systems and methods that include providing for measuring a first topographical height of a substrate at a first coordinate on the substrate and measuring a second topographical height of the substrate at a second coordinate on the substrate are provided. The measured first and second topographical heights may be provided as a wafer map. An exposure process is then performed on the substrate using the wafer map. The exposure process can include using a first focal point when exposing the first coordinate on the substrate and using a second focal plane when exposing the second coordinate on the substrate. The first focal point is determined using the first topographical height and the second focal point is determined using the second topographical height.
    Type: Application
    Filed: May 22, 2013
    Publication date: February 25, 2016
    Inventors: Jui-Ching Wu, Jeng-Horng Chen, Chia-Chen Chen, Shu-Hao Chang, Shang-Chieh Chien, Ming-Chin Chien, Anthony Yen
  • Extreme Ultraviolet Lithography Process and Mask
    Publication number: 20160048071
    Abstract: An apparatus comprises a low EUV reflectivity (LEUVR) mask. The LEUVR mask includes a low thermal expansion material (LTEM) layer; a reflective multilayer (ML) over the LTEM layer; and a patterned absorption layer over the reflective ML. The reflective ML has less than 2% EUV reflectivity.
    Type: Application
    Filed: October 26, 2015
    Publication date: February 18, 2016
    Inventors: YEN-CHENG LU, JENG-HORNG CHEN, SHINN-SHENG YU, ANTHONY YEN
  • Extreme ultraviolet lithography process and mask with reduced shadow effect and enhanced intensity
    Patent number: 9261774
    Abstract: The present disclosure provides one embodiment of an extreme ultraviolet (EUV) mask. The EUV mask includes a first state and a second state different from each other; a first main polygon and a second main polygon adjacent to the first main polygon; a plurality of sub-resolution assist polygons; and a field. Each of the first and second main polygons, the sub-resolution assist polygons, and the field has an associated state. The state assigned to the first main polygon is different from the state assigned to the second main polygon. The plurality of assist polygons are assigned a same state, which is different from a state assigned to the field.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Pellicle mounting system and method
    Patent number: 9256142
    Abstract: A pellicle mounting method is provided. The method includes aligning a mounting apparatus with a top surface of a pellicle frame, the mounting apparatus having a continuous duct extending therethrough and a plurality of contact pins projecting from the mounting apparatus. The method also includes introducing a pressurizing fluid into the continuous duct that causes each of the plurality of contact pins to engage the top surface of the pellicle frame with a substantially equal force, a combined force of the plurality of contact pins urging a bottom surface of the pellicle frame against a top surface of a photomask, the combined force being adjustable based on a pressure within the continuous duct. Further, the method includes adjusting the pressure within the continuous duct until the pressure is approximately equal to a pre-determined optimal pressure.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yeh Lee-Chih, Hsin-Chang Lee, Chia-Jen Chen, Anthony Yen, Ming-Jiun Yao
  • Method of semiconductor integrated circuit fabrication
    Patent number: 9257282
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A dielectric layer is formed over a substrate. An interlayer is formed over the dielectric layer. A first photoresist layer with a first opening is formed over the interlayer and a second photoresist layer having a second opening is formed over the first photoresist layer. Spacers are formed along sidewalls of the first opening and the second opening. A first trench is formed in the interlayer by using the spacer along the first opening as an etch mask. A second trench is formed in the interlayer by using the spacer along the second opening as an etch mask. The first trench and the second trench are extended down into the dielectric layer as a lower portion and an upper portion, respectively, of a dielectric trench.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tsung Shih, Tsung-Min Huang, Chung-Ju Lee, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Method of making an extreme ultraviolet pellicle
    Patent number: 9256123
    Abstract: The present disclosure relates to a method of forming an EUV pellicle having an pellicle film connected to a pellicle frame without a supportive mesh, and an associated apparatus. In some embodiments, the method is performed by forming a cleaving plane within a substrate at a position parallel to a top surface of the substrate. A pellicle frame is attached to the top surface of the substrate. The substrate is cleaved along the cleaving plane to form a pellicle film comprising a thinned substrate coupled to the pellicle frame. Prior to cleaving the substrate, the substrate is operated upon to reduce structural damage to the top surface of substrate during formation of the cleaving plane and/or during cleaving the substrate. Reducing structural damage to the top surface of the substrate improves the durability of the thinned substrate and removes a need for a support structure for the pellicle film.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: February 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Tsung Shih, Tien-Hsi Lee, Chia-Jen Chen, Shang-Chieh Chien, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Method to Mitigate Defect Printability for ID Pattern
    Publication number: 20160033866
    Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes loading a mask to a lithography system, wherein the mask includes an one-dimensional integrated circuit (1D IC) pattern; utilizing a pupil phase modulator in the lithography system to modulate phase of light diffracted from the mask; and performing a lithography exposing process to a target in the lithography system with the mask and the pupil phase modulator.
    Type: Application
    Filed: July 31, 2014
    Publication date: February 4, 2016
    Inventors: Yen-Cheng Lu, Chia-Hao Hsu, Shinn-Sheng Yu, Chia-Chen Chien, Jeng-Horng Chen, Anthony Yen
  • Metal and via definition scheme
    Patent number: 9252048
    Abstract: A method includes defining a photoresist layer over a first dielectric layer. The first dielectric layer is disposed over an etch stop layer and the etch stop layer is disposed over a second dielectric layer. A spacer layer is formed over the photoresist and the first dielectric layer. The spacer layer has an opening that has a via width. The opening is disposed directly above a via location. A metal trench with a metal width is formed in the first dielectric layer. The metal width at the via location is greater than the via width. A via hole with the via width is formed at the via location in the second dielectric layer.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: February 2, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Photomask and method for forming the same
    Patent number: 9244341
    Abstract: A photomask having a machine-readable identifying mark and suitable for manufacturing integrated circuit devices and a method for forming the photomask and identifying mark are disclosed. An exemplary embodiment includes receiving a design layout corresponding to a pattern to be formed on a photomask blank. A specification of an identifying code is also received along with the photomask blank, which includes a substrate, a reflective layer, and an absorptive layer. A first patterning is performed using the design layout. A second patterning is performed using the specification of the identifying code.
    Type: Grant
    Filed: February 24, 2015
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chang Lee, Chia-Jen Chen, Pei-Cheng Hsu, Anthony Yen
  • Extreme ultraviolet lithography process and mask
    Patent number: 9244366
    Abstract: An extreme ultraviolet lithography (EUVL) process is performed on a target, such as a semiconductor wafer, having a photosensitive layer. The method includes providing a one-dimensional patterned mask along a first direction. The patterned mask includes a substrate including a first region and a second region, a multilayer mirror above the first and second regions, an absorption layer above the multilayer mirror in the second region, and a defect in the first region. The method further includes exposing the patterned mask by an illuminator and setting the patterned mask and the target in relative motion along the first direction while exposing the patterned mask. As a result, an accumulated exposure dose received by the target is an optimized exposure dose.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: January 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen