Patents by Inventor Anthony Yen

Anthony Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Assist Feature for a Photolithographic Process
    Publication number: 20160011501
    Abstract: A photomask having a partial-thickness assist feature and a technique for manufacturing the photomask are disclosed. In an exemplary embodiment, the photomask includes a mask substrate, a reflective structure disposed on the mask substrate, and an absorptive layer formed on the reflective structure. A printing feature region and an assist feature region are defined on the mask. The absorptive layer has a first thickness in the printing feature region and a second thickness in the assist feature region that is different from the first thickness. In some such embodiments, the second thickness is configured such that radiation reflected by the assist feature region does not exceed an exposure threshold of a photoresist of a target.
    Type: Application
    Filed: July 10, 2014
    Publication date: January 14, 2016
    Inventors: Tao-Min HUANG, Chia-Jen CHEN, Hsin-Chang LEE, Chih-Tsung SHIH, Shinn-Sheng YU, Jeng-Horng CHEN, Anthony YEN
  • Method for integrated circuit patterning
    Patent number: 9229326
    Abstract: Provided is a method of forming a pattern for an integrated circuit. The method includes forming a first layer over a substrate, wherein the first layer's etch rate is sensitive to a radiation, such as an extreme ultraviolet (EUV) radiation or an electron beam (e-beam). The method further includes forming a resist layer over the first layer and exposing the resist layer to the radiation for patterning. During the exposure, various portions of the first layer change their etch rate in response to an energy dose of the radiation received therein. The method further includes developing the resist layer, etching the first layer, and etching the substrate to form a pattern. The radiation-sensitivity of the first layer serves to reduce critical dimension variance of the pattern.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shu-Hao Chang, Shinn-Sheng Yu, Jui-Ching Wu, Jeng-Horng Chen, Anthony Yen
  • Lithography and mask for resolution enhancement
    Patent number: 9223197
    Abstract: A lithography process in a lithography system includes loading a mask having multiple mask states and having a mask pattern consisting of a plurality of polygons and a field. Different mask states are assigned to adjacent polygons and the field. The lithography process further includes configuring an illuminator to generate an illumination pattern on an illumination pupil plane of the lithography system; configuring a pupil filter on a projection pupil plane of the lithography system with a filtering pattern determined according to the illumination pattern; and performing an exposure process to a target with the illuminator, the mask, and the pupil filter. The exposure process produces diffracted light and non-diffracted light behind the mask and the pupil filter removes most of the non-diffracted light.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: December 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shinn-Sheng Yu, Yen-Cheng Lu, Anthony Yen
  • Reflective mask and method of making same
    Patent number: 9213232
    Abstract: A reflective mask is described. The mask includes a low thermal expansion material (LTEM) substrate, a conductive layer deposited on a first surface of the LTEM substrate, a stack of reflective multilayers (ML) deposited on a second surface of the LTEM substrate, a capping layer deposited on the stack of reflective ML, a first absorption layer deposited on the first capping layer, a main pattern, and a border ditch. The border ditch reaches to the capping layer, a second absorption layer deposited inside the border ditch, and where the second absorption layer contacts the capping layer. In some instances, the border ditch crosses the capping layer and partially enters the reflective multilayer.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: December 15, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Cheng Hsu, Chih-Tsung Shih, Chia-Jen Chen, Tsiao-Chen Wu, Shinn-Sheng Yu, Hsin-Chang Lee, Anthony Yen
  • Extreme Ultraviolet Lithography Process and Mask
    Publication number: 20150346596
    Abstract: An extreme ultraviolet lithography (EUVL) process is disclosed. The process comprises receiving a mask. The mask includes a low thermal expansion material (LTEM) substrate, a reflective multilayer (ML)over one surface of the LTEM substrate, a first region having a phase-shifting layer over the reflective ML, and a second region having no phase-shifting layer over the reflective ML. The EUVL process also comprises exposing the mask by a nearly on-axis illumination with partial coherence less than 0.3 to produce diffracted light and non-diffracted light, removing at least a portion of the non-diffracted light, and collecting and directing the diffracted light and the not removed non-diffracted light by a projection optics box (POB) to expose a target.
    Type: Application
    Filed: August 14, 2015
    Publication date: December 3, 2015
    Inventors: Yen-Cheng Lu, JENG-HORNG CHEN, SHINN-SHENG YU, ANTHONY YEN
  • Method for mask fabrication and repair
    Patent number: 9195135
    Abstract: A method for repairing a phase-defect region in a patterned mask for extreme ultraviolet lithography (EUVL) is disclosed. A patterned mask for EUVL is received. The patterned mask includes an absorptive region having an absorption layer over a defect-repairing-enhancement (DRE) layer, a reflective region having the DRE layer without the absorption layer on top of it, a defect and a phase-defect region resulting from the defect and intruding the reflective region. A location and a shape of the phase-defect region is determined. A portion or portions of the DRE layer in the reflective region is removed according to the location and the shape of the phase-defect region to compensate the effect of the phase-defect region.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: November 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Extreme Ultraviolet Light (EUV) Photomasks and Fabrication Methods Thereof
    Publication number: 20150331307
    Abstract: Embodiments of EUV photomasks and methods for forming a EUV photomask are provided. The method comprises providing a substrate, a reflective layer, a capping layer, a hard mask layer, and forming an opening therein. An absorber layer is then filled in the opening and over the top surface of the hard mask layer. A removing process is provided to form an absorber with a top surface lower than a top surface of the capping layer.
    Type: Application
    Filed: July 27, 2015
    Publication date: November 19, 2015
    Inventors: Yen-Cheng Lu, Chih-Tsung Shih, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Extreme ultraviolet lithography process and mask
    Patent number: 9182659
    Abstract: A system and process of an extreme ultraviolet lithography (EUVL) is disclosed. An EUVL process includes receiving a mask pair having a same pattern. The mask pair includes an extreme ultraviolet (EUV) mask and a low EUV reflectivity mask. A first exposure process is performed by using the EUV mask to expose a substrate. A second exposure process is performed by using the low EUV reflectivity mask to expose the same substrate. The first exposure process is conducted according to a first exposure dose matrix and the second exposure process is conducted according to a second exposure dose matrix.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: November 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Method of Semiconductor Integrated Circuit Fabrication
    Publication number: 20150318173
    Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A dielectric layer is formed over a substrate. An interlayer is formed over the dielectric layer. A first photoresist layer with a first opening is formed over the interlayer and a second photoresist layer having a second opening is formed over the first photoresist layer. Spacers are formed along sidewalls of the first opening and the second opening. A first trench is formed in the interlayer by using the spacer along the first opening as an etch mask. A second trench is formed in the interlayer by using the spacer along the second opening as an etch mask. The first trench and the second trench are extended down into the dielectric layer as a lower portion and an upper portion, respectively, of a dielectric trench.
    Type: Application
    Filed: May 2, 2014
    Publication date: November 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tsung Shih, Tsung-Min Huang, Chung-Ju Lee, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • LITHOGRAPHY SYSTEM AND METHOD FOR PATTERNING PHOTORESIST LAYER ON EUV MASK
    Publication number: 20150309401
    Abstract: A lithography system for an extreme ultra violet (EUV) mask is provided. The lithography system includes a coupling module. The coupling module includes at least one mask contact element configured to touch a peripheral area of the EUV mask. The lithography system also includes an ammeter having an end electrically connected to the EUV mask through the at least one mask contact element and another end connected to a ground potential. The ammeter includes a sensor configured to measure a current conducting from the EUV mask to the ground potential and a compensation circuit configured to provide a compensation current that is opposite to the current measured by the sensor.
    Type: Application
    Filed: April 25, 2014
    Publication date: October 29, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yun-Yue LIN, Chia-Jen CHEN, Hsin-Chang LEE, Anthony YEN
  • PELLICLE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20150309404
    Abstract: A pellicle structure, a pellicle-mask structure, and a method for forming the pellicle structure are provided. The pellicle structure includes a pellicle film made of a carbon-based material. In addition, the pellicle film is configured to protect a mask structure in a lithography process. The pellicle-mask structure includes a mask substrate having a mask pattern formed over the mask substrate and the pellicle frame disposed on the mask substrate. The pellicle-mask structure further includes the pellicle film disposed on the pellicle frame.
    Type: Application
    Filed: April 24, 2014
    Publication date: October 29, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Yun-Yue LIN, Chia-Jen CHEN, Hsin-Chang LEE, Anthony YEN
  • METHOD OF MAKING AN EXTREME ULTRAVIOLET PELLICLE
    Publication number: 20150309405
    Abstract: The present disclosure relates to a method of forming an EUV pellicle having an pellicle film connected to a pellicle frame without a supportive mesh, and an associated apparatus. In some embodiments, the method is performed by forming a cleaving plane within a substrate at a position parallel to a top surface of the substrate. A pellicle frame is attached to the top surface of the substrate. The substrate is cleaved along the cleaving plane to form a pellicle film comprising a thinned substrate coupled to the pellicle frame. Prior to cleaving the substrate, the substrate is operated upon to reduce structural damage to the top surface of substrate during formation of the cleaving plane and/or during cleaving the substrate. Reducing structural damage to the top surface of the substrate improves the durability of the thinned substrate and removes a need for a support structure for the pellicle film.
    Type: Application
    Filed: April 23, 2014
    Publication date: October 29, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Tsung Shih, Benjamin Lee, Chia-Jen Chen, Shang-Chieh Chien, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Lithography layer with quenchers to prevent pattern collapse
    Patent number: 9159559
    Abstract: The present disclosure provides a method for forming resist patterns. The method includes providing a substrate; forming a material layer including a plurality of quenchers on the substrate; forming a resist layer on the material layer; exposing the resist layer; and developing the resist layer to form a structure featuring resist remaining layer on an upper surface of the material layer, and a plurality of resist features on the resist remaining layer to improve the yield of lithography process.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Chieh Chien, Shu-Hao Chang, Jui-Ching Wu, Jeng-Horng Chen, Anthony Yen
  • Method to Define Multiple Layer Patterns with a Single Exposure by Charged Particle Beam Lithography
    Publication number: 20150287596
    Abstract: The present disclosure provides a method that includes forming a first patternable material layer on a substrate; forming a second patternable material layer over the first patternable material layer; and performing a charged particle beam lithography exposure process to the first patternable material layer and the second patternable material layer, thereby forming a first latent feature in the first patternable material layer and a second latent feature in the second patternable material layer.
    Type: Application
    Filed: June 23, 2015
    Publication date: October 8, 2015
    Inventors: Yen-Cheng Lu, Chih-Tsung Shih, Jeng-Horng Chen, Shinn-Sheng Yu, Anthony Yen
  • Method and System for Reducing Pole Imbalance by Adjusting Exposure Intensity
    Publication number: 20150277234
    Abstract: A method and system for adjusting exposure intensity to reduce unwanted lithographic effects is disclosed. In some exemplary embodiments, the method of photolithography includes receiving a mask and a workpiece. An orientation of an illumination pattern relative to the mask is determined, and an intensity profile of the illumination pattern is adjusted according to the orientation. The mask is exposed to radiation according to the illumination pattern and the intensity profile. Radiation resulting from the exposing of the mask is utilized to expose the workpiece. In some such embodiments, the intensity profile includes an intensity that varies across an illuminated region of the illumination pattern.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 1, 2015
    Applicant: Taiwan Semiconductor Manufacturng Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Extreme ultraviolet lithography process and mask
    Patent number: 9146459
    Abstract: A low EUV reflectivity mask includes a low thermal expansion material (LTEM) layer, a low EUV reflectivity (LEUVR) multilayer over the LTEM layer in a first region, a high EUV reflectivity (HEUVR) multilayer over the LTEM layer in a second region and a patterned absorption layer over the LEUVR multilayer and the HEUVR multilayer.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: September 29, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Cheng Lu, Shinn-Sheng Yu, Jeng-Horng Chen, Anthony Yen
  • Method of Fabricating an Integrated Circuit with Enhanced Defect Repairability
    Publication number: 20150268561
    Abstract: The present disclosure provides one embodiment of a method for extreme ultraviolet lithography (EUVL) process. The method includes loading a mask to a lithography system. The mask includes defect-repaired regions and defines an integrated circuit (IC) pattern thereon. The method also includes setting an illuminator of the lithography system in an illumination mode according to the IC pattern, configuring a pupil filter in the lithography system according to the illumination mode and performing a lithography exposure process to a target with the mask and the pupil filter by the lithography system in the illumination mode.
    Type: Application
    Filed: March 21, 2014
    Publication date: September 24, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: YEN-CHENG LU, SHINN-SHENG YU, JENG-HORNG CHEN, ANTHONY YEN
  • LITHOGRAPHY PROCESS
    Publication number: 20150268565
    Abstract: A method for being used in a lithography process is provided. The method includes receiving a first mask, a second mask and a substrate with a set of baseline registration marks. A first set of registration marks is formed on the substrate using the first mask and a first exposure tool, and a first set of overlay errors is determined. The first set of registration marks is removed and a second set of registration marks is formed on the substrate using the second mask and a second exposure tool. A second set of overlay errors is determined. A set of tool-induced overlay errors is generated from the first and second sets of overlay errors and used in fabricating a third mask. The third mask can then be used in the lithography process to accommodate the overlay errors caused by different exposure tools, different masks, and different mask writers.
    Type: Application
    Filed: June 8, 2015
    Publication date: September 24, 2015
    Inventors: Shinn-Sheng Yu, Anthony Yen
  • Method for Integrated Circuit Patterning
    Publication number: 20150262836
    Abstract: Provided is a method of forming a pattern for an integrated circuit. The method includes forming a first layer over a substrate, wherein the first layer's etch rate is sensitive to a radiation, such as an extreme ultraviolet (EUV) radiation or an electron beam (e-beam). The method further includes forming a resist layer over the first layer and exposing the resist layer to the radiation for patterning. During the exposure, various portions of the first layer change their etch rate in response to an energy dose of the radiation received therein. The method further includes developing the resist layer, etching the first layer, and etching the substrate to form a pattern. The radiation-sensitivity of the first layer serves to reduce critical dimension variance of the pattern.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 17, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: YEN-CHENG LU, SHU-HAO CHANG, SHINN-SHENG YU, JUI-CHING WU, JENG-HORNG CHEN, ANTHONY YEN
  • Structure and Method for Reflective-Type Mask
    Publication number: 20150261082
    Abstract: A reflective mask includes a substrate; a reflective multilayer formed on the substrate; an absorber layer formed on the reflective multilayer, wherein the absorber layer is patterned to have openings according to an integrated circuit layout; and a protection layer formed over the reflective multilayer within the openings.
    Type: Application
    Filed: May 29, 2015
    Publication date: September 17, 2015
    Inventors: CHIH-TSUNG SHIH, CHI-LUN LU, JENG-HORNG CHEN, CHIA-CHEN CHEN, SHINN-SHENG YU, ANTHONY YEN, WEI-HUNG LIU