Abstract: A method detects and mitigates harm caused by electromagnetic interference (EMI) to digital transmissions within an electronic circuit. One or more processors check for an initial transmission error during an initial digital transmission between a digital transmitter and a digital receiver on an electronic circuit. In response to detecting the initial transmission error, the processor(s) receive electromagnetic interference (EMI) detection signals from one or more EMI detectors. In response to determining that the EMI detection signals represent an EMI level that exceeds a predetermined value, the processor(s) identify an EMI anomaly source on the electronic circuit and adjusts the EMI anomaly source until the EMI level has been reduced to a nominal level. A copy of the initial digital transmission is then resent from the digital transmitter to the digital receiver. If no transmission error reoccurs, then the EMI anomaly source is kept in the adjusted state.

Abstract: Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.

Abstract: A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.

Abstract: A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory cells. The memory device may also include a sense amplifier. The sense amplifier may be configured to read data from the plurality of memory cells using a reference voltage. The memory device may also include a sense amplifier reference voltage modification circuit. The sense amplifier reference voltage modification circuit may be configured to detect a triggering event and modify the reference voltage in response to detecting a triggering event.

Abstract: A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.

Abstract: A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.

Abstract: A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.

Abstract: A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.

Abstract: A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.

Abstract: A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.

Abstract: A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic.

Abstract: A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory cells. The memory device may also include a sense amplifier. The sense amplifier may be configured to read data from the plurality of memory cells using a reference voltage. The memory device may also include a sense amplifier reference voltage modification circuit. The sense amplifier reference voltage modification circuit may be configured to detect a triggering event and modify the reference voltage in response to detecting a triggering event.

Abstract: A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.

Abstract: A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.

Abstract: A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory cells. The memory device may also include a sense amplifier. The sense amplifier may be configured to read data from the plurality of memory cells using a reference voltage. The memory device may also include a sense amplifier reference voltage modification circuit. The sense amplifier reference voltage modification circuit may be configured to detect a triggering event and modify the reference voltage in response to detecting a triggering event.

Abstract: A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.

Abstract: A method, system and memory controller are provided for implementing simultaneous read and write operations in a memory subsystem utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. A DRAM includes a first partition and a second partition. A memory controller determines if memory requirements are above or below a usage threshold. If the memory requirements are below the usage threshold, the memory is partitioned into a read buffer and a write buffer, with writes going to the write buffer and reads coming from the read buffer, data being transferred from the write buffer to the read buffer through an Error Correction Code (ECC) engine. If the memory requirements are above the usage threshold, the entire memory is used for reads and writes.

Abstract: Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.

Abstract: A method, system and computer program product are provided for implementing hardware assisted Dynamic Random Access Memory (DRAM) repair in a computer system that supports ECC. A data register providing DRAM repair is selectively provided in one of the Dynamic Random Access Memory (DRAM), a memory controller, or a memory buffer coupled between the DRAM and the memory controller. The data register is configured to map to any address. Responsive to the configured address being detected, the reads to or the writes from the configured address are routed to the data register.

Abstract: A refresh command is communicated to a memory device to initiate an interruptible refresh which contains multiple segment refreshes separated by interrupt boundaries. A command is communicated to the memory device before execution of a segment refresh and the segment refresh is delayed at an interrupt boundary. Alternatively, a first number of commands in a queue is determined. A first number of segment refreshes to execute is determined based on the first number of commands. The first number of segment refreshes to execute is communicated to the memory device to cause execution of the first number of segment refreshes. A second number of commands in the queue is determined. A second number of segment refreshes to execute is determined based on the second number of commands. The second number of segment refreshes to execute is communicated to the memory device to cause execution of the second number of segment refreshes.