Abstract: Provided are methods for forming an electrically conductive structure of a desired three-dimensional shape on a substantially planar surface of a substrate, e.g., a semiconductor wafer. Typically, the particulate matter is deposited in a layer-by-layer manner and adhered to selected regions on the substrate surface. The particulate matter may be deposited to produce a mold for forming the structure and/or to produce the structure itself. A three-dimensional printer with associated electronic data may be used without the need of a lithographic mask or reticle.

Abstract: Provided are systems and processes for forming a three-dimensional circuit on a substrate. A radiation source produces a beam that is directed at a substrate having an isolating layer interposed between circuit layers. The circuit layers communicate with reach other via a seed region exhibiting a crystalline surface. At least one circuit layer has an initial microstructure that exhibits electronic properties unsuitable for forming circuit features therein. After being controllably heat treated, the initial microstructure of the circuit layer having unsuitable properties is transformed into one that exhibits electronic properties suitable for forming circuit feature therein. Also provided are three-dimensional circuit structures optionally formed by the inventive systems and/or processes.

Abstract: Provided are systems and processes for forming a three-dimensional circuit on a substrate. A radiation source produces a beam that is directed at a substrate having an isolating layer interposed between circuit layers. The circuit layers communicate with reach other via a seed region exhibiting a crystalline surface. At least one circuit layer has an initial microstructure that exhibits electronic properties unsuitable for forming circuit features therein. After being controllably heat treated, the initial microstructure of the circuit layer having unsuitable properties is transformed into one that exhibits electronic properties suitable for forming circuit feature therein. Also provided are three-dimensional circuit structures optionally formed by the inventive systems and/or processes.

Abstract: Provided are apparatuses and method for the thermal processing of a substrate surface, e.g., controlled laser thermal annealing (LTA) of substrates. The invention typically involves irradiating the substrate surface with first and second images to process regions of the substrate surface at a substantially uniform peak processing temperature along a scan path. A first image may serve to effect spike annealing of the substrates while another may be used to provide auxiliary heat treatment to the substrates before and/or after the spike annealing. Control over the temperature profile of the prespike and/or postspike may also reduce stresses and strains generated in the wafers. Also provided are microelectronic devices formed using the inventive apparatuses and methods.

Abstract: Provided are methods for forming an electrically conductive structure of a desired three-dimensional shape on a substantially planar surface of a substrate, e.g., a semiconductor wafer. Typically, the particulate matter is deposited in a layer-by-layer manner and adhered to selected regions on the substrate surface. The particulate matter may be deposited to produce a mold for forming the structure and/or to produce the structure itself. A three-dimensional printer with associated electronic data may be used without the need of a lithographic mask or reticle.

Abstract: An integrated wafer processing system having a wafer queuing station and a plurality of plasma reactors connected to peripheral walls of a central vacuum chamber. Vacuum valves separate the central chamber from the queuing station and the plasma reactors. A wafer transfer arm capable of R-&THgr; motion can transfer wafers between the queuing station and any of the plasma reactors in either a single-step or a multi-step process.

Abstract: An integrated wafer processing system having a wafer queuing station and a plurality of plasma reactors connected to peripheral walls of a central vacuum chamber. Vacuum valves separate the central chamber from the queuing station and the plasma reactors. A wafer transfer arm capable of R-&THgr; motion can transfer wafers between the queuing station and any of the plasma reactors in either a single-step or a multi-step process.

Abstract: An integrated wafer processing system having a wafer queuing station and a plurality of plasma reactors connected to peripheral walls of a central vacuum chamber. Vacuum valves separate the central chamber from the queuing station and the plasma reactors. A wafer transfer arm capable of R-&THgr; motion can transfer wafers between the queuing station and any of the plasma reactors in either a single-step or a multi-step process.

Abstract: An integrated wafer processing system having a wafer queuing station and a plurality of plasma reactors connected to peripheral walls of a central vacuum chamber. Vacuum valves separate the central chamber from the queuing station and the plasma reactors. A wafer transfer arm capable of R-&THgr; motion can transfer wafers between the queuing station and any of the plasma reactors in either a single-step or a multi-step process.

Abstract: The present invention includes plural plasma processing vessels and a wafer queuing station arrayed with a wafer transfer arm in a controlled environment. Wafers are movable within the controlled environment one at a time selectably between the several plasma vessels and the wafer queuing station without atmospheric or other exposure so that possible contamination of the moved wafers is prevented. The system is selectively operative in either single-step or multiple-step processing modes, and in either of the modes, the several plasma etching vessels are operable to provide a desirably high system throughput. In the preferred embodiment, the several plasma vessels and the queuing station are arrayed about a closed pentagonal locus with the wafer transfer arm disposed within the closed locus.

Abstract: A substrate processing system is provided that includes substrate processing vessels, a substrate queuing station, a substrate transfer device, and a processor. The processor, in communication with the processing vessels, the queuing station, and the transfer device, provides selectable single and multi-step processing of the substrates by accessing a process command for a given substrate corresponding to desired processing of the substrate.

Abstract: The present invention includes plural plasma etching vessels and a wafer queuing station arrayed with a wafer transfer arm in a controlled environment. Wafers are movable within the controlled environment one at a time selectably between the several plasma vessels and the wafer queuing station without atmospheric or other exposure so that possible contamination of the moved wafers is prevented. The system is selectively operative in either single-step or multiple-step processing modes, and in either of the modes, the several plasma etching vessels are operable to provide a desirably high system throughput. In the preferred embodiment, the several plasma vessels and the queuing station are arrayed about a closed pentagonal locus with the wafer transfer arm disposed within the closed locus.

Abstract: The present invention includes plural plasma etching vessels and a wafer queuing station arrayed with a wafer transfer arm in a controlled environment. Wafers are movable within the controlled environment one at a time selectably between the plasma vessels and the wafer queuing station without atmospheric or other possible contamination. The system is selectively operative in either single-step or multiple-step processing modes. In the preferred embodiment, the plasma vessels and the queuing station are arrayed about a closed pentagonal locus with the wafer transfer arm disposed within the closed locus. The wafer transfer arm is movable between the plasma etching vessels and the wafer queuing station. Selectably actuable vacuum locks are provided between the plasma etching vessels and the wafer transfer arm to maintain an intended atmospheric condition and to allow wafer transport therethrough. The plasma vessels each include first and second water-cooled electrodes that are movable relatively to each other.

Abstract: Plural plasma etching vessels and a wafer queuing station are arrayed about a closed pentagonal locus with a wafer transfer arm therewithin all in a controlled vacuum environment. Wafers are movable within the controlled environment between the several plasma vessels and the wafer queuing station without atmospheric or other exposure so that possible contamination of the moved wafers is prevented. The system is selectively operative in either single-step or multiple-step processing modes, and in either of the modes, the several plasma etching vessels are operable to provide a desirably high system throughput. Wafer processing in each vessel is regulated by a state controller for processing a plurality of wafers from a single cassette, contained within the vacuum environment of the plural plasma etching vessels and wafer queuing station, to provide an orderly and efficient throughput of wafers for diverse or similar processing in the plural vessels. The wafer transfer arm is movable in R and .theta..

Abstract: The present invention includes plural plasma etching vessels and a wafer queuing station arrayed with a wafer transfer arm in a controlled environment. Wafers are movable within the controlled environment one at a time selectably between the several plasma vessels and the wafer queuing station without atmospheric or other exposure to that possible contamination of the moved wafers is prevented. The system is selectively operative in either single-step or multiple-step processing modes, and in either of the modes, the several plasma etching vessels are operable to provide a desirably high system throughput. In the preferred embodiment, the several plasma vessels and the queuing station are arrayed about a closed pentagonal locus with the wafer transfer arm disposed within the closed locus.

Abstract: The present invention includes plural plasma etching vessels and a wafer queuing station arrayed with a wafer transfer arm in a controlled environment. Wafer processing in each vessel is regulated by a state controller for processing a plurality of wafers from a single cassette, contained within the vacuum environment of the plural plasma etching vessels and wafer queuing station, to provide an orderly and efficient throughput of wafers for diverse or similar processing in the plural vessels. In this manner a wafer can be processed as soon as a vessel becomes available.

Abstract: Method and apparatus for masked etching of a polysilicon surface layer or film to expose a dielectric underlying layer or film on a semiconductor material using ion bombardment from an ionized mixture of a fluorine based gas with a chlorine or bromine containing gas. A particularly useful gas is a mixture of sulfur hexafluoride and Freon 115 gases (C.sub.2 ClF.sub.5). The mixture of gases achieves the result of highly selective etching through the polysilicon film without significantly attacking the underlying dielectric film and without significant undercutting in the polysilicon film or etching of the masking layer.

Abstract: Dry plasma etching of a plurality of planar thin-film semiconductor wafers is effected simultaneously and uniformly in a relatively small chamber enveloping a vertically-stacked array of laminar electrode sub-assemblies each of which includes a pair of oppositely-excited electrode plates tightly sandwiching a solid insulating layer of dielectric material, the parallel sub-assemblies being vertically separated to subdivide the chamber into a plurality of reactor regions where RF discharges can excite a normally inert ambient gas to develop reactive plasma for simultaneous planar plasma etching or reactive ion etching (RIE) of all wafers within the several regions.