Patents by Inventor Atapol Prajuckamol
Atapol Prajuckamol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220246486Abstract: Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate and a plurality of press-fit pins. The press-fit pins are molded into and fixedly coupled with the case. The pins are also electrically and mechanically coupled to the substrate.Type: ApplicationFiled: April 22, 2022Publication date: August 4, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang YAO, Chee CHEW, Atapol PRAJUCKAMOL
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Patent number: 11374373Abstract: A press-fit pin for a semiconductor package includes a shaft terminating in a head. A pair of arms extends away from a center of the head. Each arm includes a curved shape and the arms together form an s-shape. A length of the s-shape is longer than the shaft diameter. An outer extremity of each arm includes a contact surface configured to electrically couple to and form a friction fit with a pin receiver. In implementations the press-fit pin has only two surfaces configured to contact an inner sidewall of the pin receiver and is configured to contact the inner sidewall at only two locations. The shaft may be a cylinder. The s-shape formed by the pair of arms is visible from a view facing a top of the press-fit pin along a direction parallel with the longest length of the shaft. Versions include a through-hole extending through the head.Type: GrantFiled: May 13, 2020Date of Patent: June 28, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chee Hiong Chew, Atapol Prajuckamol, Yusheng Lin
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Publication number: 20220199502Abstract: Implementations of a semiconductor package may include a first substrate including a first group of leads physically coupled thereto and a second group of leads physically coupled thereto; a second substrate coupled over the first substrate and physically coupled to the first group of leads and the second group of leads; and one or more semiconductor die coupled between the first substrate and the second substrate. The second group of leads may be electrically isolated from the first substrate.Type: ApplicationFiled: December 18, 2020Publication date: June 23, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, Chee Hiong CHEW, Yusheng LIN
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Patent number: 11342237Abstract: Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate and a plurality of press-fit pins. The press-fit pins are molded into and fixedly coupled with the case. The pins are also electrically and mechanically coupled to the substrate.Type: GrantFiled: April 22, 2016Date of Patent: May 24, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang Yao, Chee Hiong Chew, Atapol Prajuckamol
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Publication number: 20220159853Abstract: In one embodiment, a semiconductor package may be formed having a first side and a second side that is substantially opposite to the first side. An embodiment may include forming an attachment clip extending substantially laterally between the first and second sides wherein the attachment clip is positioned near a distal end of the first and second sides. An embodiment may also include forming the attachment clip to have a flexible main portion that can bend away from a plane of the main portion toward a bottom side of the semiconductor package.Type: ApplicationFiled: January 31, 2022Publication date: May 19, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, Yushuang YAO, Chee Hiong CHEW
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Patent number: 11272625Abstract: In one embodiment, a semiconductor package may be formed having a first side and a second side that is substantially opposite to the first side. An embodiment may include forming an attachment clip extending substantially laterally between the first and second sides wherein the attachment clip is positioned near a distal end of the first and second sides. An embodiment may also include forming the attachment clip to have a flexible main portion that can bend away from a plane of the main portion toward a bottom side of the semiconductor package.Type: GrantFiled: April 4, 2018Date of Patent: March 8, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol Prajuckamol, Chee Hiong Chew, Yushuang Yao
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Patent number: 11217506Abstract: In a general aspect, a semiconductor device assembly can include a substrate, a semiconductor die disposed on the substrate, a thermally conductive spacer having a first side and a second side, the second side being opposite the first side. The first side of the thermally conductive spacer can include a plurality of steps that are coupled with the substrate. The first side of the thermally conductive spacer can also include a surface that is disposed between the plurality of steps, where the surface can be coupled with the semiconductor die.Type: GrantFiled: December 19, 2019Date of Patent: January 4, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol Prajuckamol, Chee Hiong Chew
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Patent number: 11081828Abstract: A housing that can be used for a power module in a power system is disclosed. The housing includes features to improve the insulating properties and to reduce or eliminate a mechanical stress on a housing that could crack or break a substrate contained within the housing. The insulating properties are improved by protrusions that surround apertures for press-fit pins. Each protrusion can increase a creepage for the housing by extending the surface of the housing along a press-fit pin. The mechanical stress is reduced by a mounting flange that includes a wedge surface and a flexible structure that react to a force applied when the mounting flange is fastened to a surface by a fastener.Type: GrantFiled: July 12, 2019Date of Patent: August 3, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jihwan Kim, Yushuang Yao, Bosung Won, Atapol Prajuckamol, Olaf Zschieschang
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Publication number: 20210219448Abstract: A fin frame baseplate is disclosed. Specific implementations include a baseplate configured to be coupled to a substrate, a fin frame including a base portion coupled to the baseplate, and a plurality of fins extending from the base portion, the plurality of fins protruding from the base portion. The fin frame may include a plurality of openings therethrough.Type: ApplicationFiled: March 29, 2021Publication date: July 15, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, Chee Hiong CHEW, Yushuang YAO
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Publication number: 20210193551Abstract: In a general aspect, a semiconductor device assembly can include a substrate, a semiconductor die disposed on the substrate, a thermally conductive spacer having a first side and a second side, the second side being opposite the first side. The first side of the thermally conductive spacer can include a plurality of steps that are coupled with the substrate. The first side of the thermally conductive spacer can also include a surface that is disposed between the plurality of steps, where the surface can be coupled with the semiconductor die.Type: ApplicationFiled: December 19, 2019Publication date: June 24, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, Chee Hiong CHEW
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Patent number: 10971429Abstract: Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.Type: GrantFiled: February 24, 2020Date of Patent: April 6, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol Prajuckamol, Soon Wei Wang, Hoe Kit Liew How Kiat Ley
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Patent number: 10971428Abstract: A semiconductor baseplate is disclosed. Specific implementations of a baseplate may include a planar portion including a plurality of recesses therein, the planar portion may be made of a first material, and a plurality of pegs where each peg of the plurality of pegs may be configured to fit within each recess of the plurality of recesses, the plurality of pegs may be made of a second material, where the first material and the second material may be bonded together.Type: GrantFiled: June 20, 2019Date of Patent: April 6, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol Prajuckamol, Francis J. Carney, Chee Hiong Chew, Yushuang Yao
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Patent number: 10966335Abstract: A fin frame baseplate is disclosed. Specific implementations include a baseplate configured to be coupled to a substrate, a fin frame including a base portion coupled to the baseplate, and a plurality of fins extending from the base portion, the plurality of fins protruding from the base portion. The fin frame may include a plurality of openings therethrough.Type: GrantFiled: September 30, 2019Date of Patent: March 30, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol Prajuckamol, Chee Hiong Chew, Yushuang Yao
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Publication number: 20210090975Abstract: A semiconductor package assembly having a connecting clip disposed on both a first material stack and a second material stack having different thicknesses and disposed on a conducting substrate. This connecting clip has a first portion disposed on to the first material stack and second portion disposed on the second material stack, such that the surfaces of the first portion and second portion opposite the conducting substrate are at the same perpendicular distance from the conducting substrate. For example, in some implementations, when the thickness of the second material stack is smaller than the thickness of the first material stack, the second portion of the connecting clip may include a vertical support disposed on the second material stack to equalize the heights of the surfaces of the first portion and second portion of the connecting clip.Type: ApplicationFiled: December 3, 2020Publication date: March 25, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, Chee Hiong CHEW, Yushuang YAO
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Publication number: 20210050272Abstract: Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate, and a plurality of press-fit pins. The plurality of press-fit pins may be fixedly coupled with the case. The plurality of press-fit pins may have at least one locking portion that extends from a side of the plurality of press-fit pins into the case and the plurality of press-fit pins may be electrically and mechanically coupled to the substrate.Type: ApplicationFiled: November 2, 2020Publication date: February 18, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang YAO, Chee Hiong CHEW, Atapol PRAJUCKAMOL
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Publication number: 20210035956Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.Type: ApplicationFiled: November 8, 2019Publication date: February 4, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chee Hiong CHEW, Atapol PRAJUCKAMOL, Stephen ST. GERMAIN, Yusheng LIN
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Publication number: 20210035892Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.Type: ApplicationFiled: January 3, 2020Publication date: February 4, 2021Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chee Hiong CHEW, Atapol PRAJUCKAMOL, Stephen ST. GERMAIN, Yusheng LIN
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Patent number: 10897821Abstract: One illustrative method embodiment includes: providing a direct bonded copper (DBC) substrate including a plurality of copper traces; providing a guide plate having protrusions on a surface of the guide plate; mounting hollow bush rings onto the protrusions; mounting the bush rings onto the copper traces by aligning the protrusions of the guide plate with solder units on said copper traces; attaching the bush rings and one or more dies to the copper traces by simultaneously reflowing said solder units and other solder units positioned between the dies and the copper traces; and after said simultaneous reflow, removing the protrusions from the bush rings.Type: GrantFiled: December 12, 2018Date of Patent: January 19, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang Yao, Atapol Prajuckamol, Chee Hiong Chew, Francis J. Carney, Yusheng Lin
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Publication number: 20200402887Abstract: A semiconductor baseplate is disclosed. Specific implementations of a baseplate may include a planar portion including a plurality of recesses therein, the planar portion may be made of a first material, and a plurality of pegs where each peg of the plurality of pegs may be configured to fit within each recess of the plurality of recesses, the plurality of pegs may be made of a second material, where the first material and the second material may be bonded together.Type: ApplicationFiled: June 20, 2019Publication date: December 24, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, Francis J. CARNEY, Chee Hiong CHEW, Yushuang YAO
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Patent number: D922329Type: GrantFiled: July 12, 2019Date of Patent: June 15, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jihwan Kim, Yushuang Yao, Bosung Won, Atapol Prajuckamol, Olaf Zschieschang