Patents by Inventor Atapol Prajuckamol
Atapol Prajuckamol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10861767Abstract: Example implementations relate to an electronic module can include a first direct bonded metal (DBM) substrate, a second DBM substrate, a housing member, and a plurality of connection terminals. The first DBM substrate and second DBM substrate can be aligned along a same plane. The housing member can be coupled to the first substrate and the second substrate and the housing member can include a plurality of openings in a surface of the housing member. The plurality of connection terminals can be electrically coupled to at least one of the first DBM substrate and the second DBM substrate, in which a connection terminal from the plurality of terminals can extend through an opening from the plurality of openings of the housing member.Type: GrantFiled: May 30, 2018Date of Patent: December 8, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol Prajuckamol, Chee Hiong Chew, Yushuang Yao
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Patent number: 10861775Abstract: A semiconductor package assembly having a connecting clip disposed on both a first material stack and a second material stack having different thicknesses and disposed on a conducting substrate. This connecting clip has a first portion disposed on to the first material stack and second portion disposed on the second material stack, such that the surfaces of the first portion and second portion opposite the conducting substrate are at the same perpendicular distance from the conducting substrate. For example, in some implementations, when the thickness of the second material stack is smaller than the thickness of the first material stack, the second portion of the connecting clip may include a vertical support disposed on the second material stack to equalize the heights of the surfaces of the first portion and second portion of the connecting clip.Type: GrantFiled: September 28, 2018Date of Patent: December 8, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol Prajuckamol, Chee Hiong Chew, Yushuang Yao
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Publication number: 20200373231Abstract: A semiconductor guide pin is disclosed. Specific implementations may include a heatsink, one or more substrates coupled together, one or more pressfit pins coupled to the one or more substrates, and two or more guide pins coupled to the one or more substrates, where the two or more guide pins may have a height greater than the one or more pressfit pins.Type: ApplicationFiled: July 3, 2019Publication date: November 26, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chee Hiong CHEW, Yushuang YAO, Atapol PRAJUCKAMOL, Chuncao NIU
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Publication number: 20200358221Abstract: A housing that can be used for a power module in a power system is disclosed. The housing includes features to improve the insulating properties and to reduce or eliminate a mechanical stress on a housing that could crack or break a substrate contained within the housing. The insulating properties are improved by protrusions that surround apertures for press-fit pins. Each protrusion can increase a creepage for the housing by extending the surface of the housing along a press-fit pin. The mechanical stress is reduced by a mounting flange that includes a wedge surface and a flexible structure that react to a force applied when the mounting flange is fastened to a surface by a fastener.Type: ApplicationFiled: July 12, 2019Publication date: November 12, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jihwan KIM, Yushuang YAO, Bosung WON, Atapol PRAJUCKAMOL, Olaf ZSCHIESCHANG
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Patent number: 10825748Abstract: Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate, and a plurality of press-fit pins. The plurality of press-fit pins may be fixedly coupled with the case. The plurality of press-fit pins may have at least one locking portion that extends from a side of the plurality of press-fit pins into the case and the plurality of press-fit pins may be electrically and mechanically coupled to the substrate.Type: GrantFiled: November 2, 2016Date of Patent: November 3, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang Yao, Chee Hiong Chew, Atapol Prajuckamol
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Publication number: 20200344905Abstract: A fin frame baseplate is disclosed. Specific implementations include a baseplate configured to be coupled to a substrate, a fin frame including a base portion coupled to the baseplate, and a plurality of fins extending from the base portion, the plurality of fins protruding from the base portion. The fin frame may include a plurality of openings therethrough.Type: ApplicationFiled: September 30, 2019Publication date: October 29, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, Chee Hiong CHEW, Yushuang YAO
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Publication number: 20200274310Abstract: A press-fit pin for a semiconductor package includes a shaft terminating in a head. A pair of arms extends away from a center of the head. Each arm includes a curved shape and the arms together form an s-shape. A length of the s-shape is longer than the shaft diameter. An outer extremity of each arm includes a contact surface configured to electrically couple to and form a friction fit with a pin receiver. In implementations the press-fit pin has only two surfaces configured to contact an inner sidewall of the pin receiver and is configured to contact the inner sidewall at only two locations. The shaft may be a cylinder. The s-shape formed by the pair of arms is visible from a view facing a top of the press-fit pin along a direction parallel with the longest length of the shaft. Versions include a through-hole extending through the head.Type: ApplicationFiled: May 13, 2020Publication date: August 27, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chee Hiong CHEW, Atapol PRAJUCKAMOL, Yusheng LIN
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Patent number: 10720725Abstract: Implementations of pins for semiconductor packages may include: an upper contact portion having a contact surface coupled with a pin receiver; a lower portion having a vertical stop and at least two curved legs; a horizontal base coupled directly to the at least two curved legs and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate, the horizontal base having an upper contact surface, and; a gap between a bottom contact surface of the vertical stop and the upper contact surface of the horizontal base.Type: GrantFiled: February 6, 2020Date of Patent: July 21, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang Yao, Chee Hiong Chew, Atapol Prajuckamol
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Patent number: 10699989Abstract: Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the electrically insulative layer coupled to a lead frame, and at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the second side of the electrically insulative layer into the electrically insulative layer from the lead frame. The die may be wire bonded to the lead frame.Type: GrantFiled: July 10, 2018Date of Patent: June 30, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol Prajuckamol, Sw Wang, Kai Chat Tan
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Patent number: 10693270Abstract: A press-fit pin for a semiconductor package includes a shaft terminating in a head. A pair of arms extends away from a center of the head. Each arm includes a curved shape and the arms together form an s-shape. A length of the s-shape is longer than the shaft diameter. An outer extremity of each arm includes a contact surface configured to electrically couple to and form a friction fit with a pin receiver. In implementations the press-fit pin has only two surfaces configured to contact an inner sidewall of the pin receiver and is configured to contact the inner sidewall at only two locations. The shaft may be a cylinder. The s-shape formed by the pair of arms is visible from a view facing a top of the press-fit pin along a direction parallel with the longest length of the shaft. Versions include a through-hole extending through the head.Type: GrantFiled: December 28, 2016Date of Patent: June 23, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chee Hiong Chew, Atapol Prajuckamol, Yusheng Lin
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Publication number: 20200194340Abstract: Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.Type: ApplicationFiled: February 24, 2020Publication date: June 18, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, Soon Wei WANG, Hoe Kit Liew How Kat LEY
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Publication number: 20200176907Abstract: Implementations of pins for semiconductor packages may include: an upper contact portion having a contact surface coupled with a pin receiver; a lower portion having a vertical stop and at least two curved legs; a horizontal base coupled directly to the at least two curved legs and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate, the horizontal base having an upper contact surface, and; a gap between a bottom contact surface of the vertical stop and the upper contact surface of the horizontal base.Type: ApplicationFiled: February 6, 2020Publication date: June 4, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang YAO, Chee Hiong CHEW, Atapol PRAJUCKAMOL
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Publication number: 20200105648Abstract: A semiconductor package assembly having a connecting clip disposed on both a first material stack and a second material stack having different thicknesses and disposed on a conducting substrate. This connecting clip has a first portion disposed on to the first material stack and second portion disposed on the second material stack, such that the surfaces of the first portion and second portion opposite the conducting substrate are at the same perpendicular distance from the conducting substrate. For example, in some implementations, when the thickness of the second material stack is smaller than the thickness of the first material stack, the second portion of the connecting clip may include a vertical support disposed on the second material stack to equalize the heights of the surfaces of the first portion and second portion of the connecting clip.Type: ApplicationFiled: September 28, 2018Publication date: April 2, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, Chee Hiong CHEW, Yushuang YAO
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Patent number: 10607920Abstract: Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.Type: GrantFiled: November 30, 2018Date of Patent: March 31, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol Prajuckamol, Soon Wei Wang, Hoe Kit Liew How Kat Ley
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Patent number: 10607921Abstract: Implementations of semiconductor packages may include a die including a first side and a second side opposing the first side, the second side of the die coupled to a layer, a first end of a plurality of wires each bonded to the first side of the die, a mold compound encapsulating the die and the plurality of wires, and a second end of the plurality of wires each directly bonded to one of a plurality of bumps, wherein a surface of the layer is exposed through the mold compound.Type: GrantFiled: November 30, 2018Date of Patent: March 31, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol Prajuckamol, Soon Wei Wang, Hoe Kit Liew How Kat Ley
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Patent number: 10559905Abstract: Implementations of pins for semiconductor packages may include: an upper contact portion having a contact surface configured to mechanically and electrically couple with a pin receiver; a lower portion having a vertical stop and at least two curved legs; a horizontal base coupled directly to the at least two curved legs and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate, the horizontal base having an upper contact surface, and; a gap between a bottom contact surface of the vertical stop and the upper contact surface of the horizontal base; wherein the at least two curved legs are configured to flex to allow the bottom contact surface of the vertical stop to move toward the upper contact surface of the horizontal base in response to a pressure applied to the pin along a direction collinear with a longest length of the pin toward the upper contact surface, and; wherein the vertical stop is configured to stop movement of the pin when the bottom contact sType: GrantFiled: January 16, 2019Date of Patent: February 11, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang Yao, Chee Hiong Chew, Atapol Prajuckamol
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Publication number: 20190348342Abstract: Example implementations relate to an electronic module can include a first direct bonded metal (DBM) substrate, a second DBM substrate, a housing member, and a plurality of connection terminals. The first DBM substrate and second DBM substrate can be aligned along a same plane. The housing member can be coupled to the first substrate and the second substrate and the housing member can include a plurality of openings in a surface of the housing member. The plurality of connection terminals can be electrically coupled to at least one of the first DBM substrate and the second DBM substrate, in which a connection terminal from the plurality of terminals can extend through an opening from the plurality of openings of the housing member.Type: ApplicationFiled: May 30, 2018Publication date: November 14, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, Chee Hiong CHEW, Yushuang YAO
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Patent number: 10319659Abstract: Implementations of semiconductor packages may include: a substrate comprising a first side and a second side and a hole in the substrate. The hole extending from the first side to the second side of the substrate and positioned in a center of the substrate. The semiconductor packages may also include a bushing around the hole to the first side of the substrate. The semiconductor packages may also include a plurality of pin holders arranged and coupled on the substrate. The semiconductor package may also include a molding compound at least partially encapsulating the substrate, encapsulating a side surface of the bushing, and encapsulating a plurality of side surfaces of the plurality of pin holders.Type: GrantFiled: October 13, 2017Date of Patent: June 11, 2019Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol Prajuckamol, C H Chew, Yushuang Yao
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Publication number: 20190173215Abstract: Implementations of pins for semiconductor packages may include: an upper contact portion having a contact surface configured to mechanically and electrically couple with a pin receiver; a lower portion having a vertical stop and at least two curved legs; a horizontal base coupled directly to the at least two curved legs and configured to be soldered to a substrate to mechanically and electrically couple the pin to the substrate, the horizontal base having an upper contact surface, and; a gap between a bottom contact surface of the vertical stop and the upper contact surface of the horizontal base; wherein the at least two curved legs are configured to flex to allow the bottom contact surface of the vertical stop to move toward the upper contact surface of the horizontal base in response to a pressure applied to the pin along a direction collinear with a longest length of the pin toward the upper contact surface, and; wherein the vertical stop is configured to stop movement of the pin when the bottom contact sType: ApplicationFiled: January 16, 2019Publication date: June 6, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Yushuang YAO, Chee Hiong CHEW, Atapol PRAJUCKAMOL
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Publication number: 20190122963Abstract: Implementations of a semiconductor package may include a first side of a die coupled to a first side of an electrically insulative layer, a second side of the electrically insulative layer coupled to a lead frame, and at least one ground stud physically coupled to the lead frame and to the die, the at least one ground stud extending from the second side of the electrically insulative layer into the electrically insulative layer from the lead frame. The die may be wire bonded to the lead frame.Type: ApplicationFiled: July 10, 2018Publication date: April 25, 2019Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Atapol PRAJUCKAMOL, Sw WANG, Kai Chat TAN