Patents by Inventor Atsushi Murakoshi
Atsushi Murakoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11871574Abstract: A semiconductor memory device according to an embodiment includes: a first interlayer insulating layer and a second interlayer insulating layer that are arranged in a first direction; a gate electrode layer provided between the first interlayer insulating layer and the second interlayer insulating layer; a semiconductor layer extending in the first direction and facing the gate electrode layer in a second direction intersecting the first direction; a first insulating layer provided between the gate electrode layer and the semiconductor layer; a charge storage layer provided between the gate electrode layer and the first insulating layer and containing a metal element; a second insulating layer provided between the gate electrode layer and the charge storage layer; and a first region provided between the charge storage layer and the first insulating layer and containing manganese (Mn), silicon (Si), and oxygen (O).Type: GrantFiled: September 10, 2021Date of Patent: January 9, 2024Assignee: Kioxia CorporationInventors: Atsushi Murakoshi, Tomoya Kawai
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Publication number: 20230413554Abstract: According to one embodiment, a semiconductor device includes a stacked body of alternating conductor layers and insulator layers stacked in a first direction and a columnar body extending through the stacked body in the first direction. The columnar body includes a first insulating layer extending in the first direction and comprising aluminum and oxygen, a semiconductor layer between the first insulating layer and the conductor layers of the stacked body, a charge storage film between the semiconductor layer and the conductor layers, and a second insulating layer between the semiconductor layer and the first insulating layer and comprising silicon and oxygen. An interface between the semiconductor layer and the second insulating layer contains nitrogen to eliminate defects which may reduce channel mobility or the like.Type: ApplicationFiled: March 1, 2023Publication date: December 21, 2023Inventors: Yusuke NAKAJIMA, Akira TAKASHIMA, Tsunehiro INO, Atsushi MURAKOSHI, Masaki NOGUCHI
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Publication number: 20220302140Abstract: A semiconductor memory device according to an embodiment includes: a first interlayer insulating layer and a second interlayer insulating layer that are arranged in a first direction; a gate electrode layer provided between the first interlayer insulating layer and the second interlayer insulating layer; a semiconductor layer extending in the first direction and facing the gate electrode layer in a second direction intersecting the first direction; a first insulating layer provided between the gate electrode layer and the semiconductor layer; a charge storage layer provided between the gate electrode layer and the first insulating layer and containing a metal element; a second insulating layer provided between the gate electrode layer and the charge storage layer; and a first region provided between the charge storage layer and the first insulating layer and containing manganese (Mn), silicon (Si), and oxygen (O).Type: ApplicationFiled: September 10, 2021Publication date: September 22, 2022Applicant: Kioxia CorporationInventors: Atsushi MURAKOSHI, Tomoya KAWAI
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Patent number: 10903228Abstract: A semiconductor storage device includes a semiconductor substrate and a plurality of first wiring layers stacked above the semiconductor substrate in a first direction orthogonal to the semiconductor substrate, and extending in a second direction intersecting the first direction and parallel to the semiconductor substrate. The device further includes a first memory pillar including a semiconductor layer and a first insulation layer extending in the first direction, the first insulation layer provided between the plurality of first wiring layers and the semiconductor layer so as to contact the semiconductor layer, and charge storage layers provided respectively between the plurality of first wiring layers and the first insulation layer. One or more of the charge storage layers is in contact with the first insulation layer. A plurality of second insulation layers is provided between each of the plurality of first wiring layers and each of the charge storage layers.Type: GrantFiled: August 27, 2018Date of Patent: January 26, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroki Sasaki, Atsushi Murakoshi, Ryuji Ohba
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Patent number: 10818688Abstract: A storage device includes: a plurality of electrode films stacked in a first direction, and extending in a second direction intersecting the first direction; a first semiconductor film provided adjacent to the plurality of electrode films, and extending in the first direction; a first charge holding film provided between one electrode film among the plurality of electrode films, and the semiconductor film, and including any one of a metal, a metal compound, and a high dielectric material; and a second semiconductor film located between the first semiconductor film and the charge holding film, and extending in the first direction along the first semiconductor film. The second semiconductor film is electrically insulated from the plurality of electrode films, the first charge holding film, and the first semiconductor film.Type: GrantFiled: September 6, 2018Date of Patent: October 27, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Atsushi Murakoshi, Hiroki Sasaki
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Patent number: 10541311Abstract: In a semiconductor memory device, first insulating films are arranged along a first direction and a second direction and extend in a third direction. Interconnect is disposed between the first insulating films in the first direction and extends in the third direction. Electrodes are disposed between the first insulating films in the first direction on a second direction side of the interconnect, and is arranged along the third direction. Second insulating film is disposed between the interconnect and the electrodes. Semiconductor members are arranged along the third direction between the first insulating films in the second direction and extend in the first direction. The electrode is disposed between the interconnect and the semiconductor members. Third insulating film is disposed between the electrodes and the semiconductor member and is thicker than the second insulating film.Type: GrantFiled: September 13, 2016Date of Patent: January 21, 2020Assignee: Toshiba Memory CorporationInventors: Katsuyuki Sekine, Tatsuya Kato, Fumitaka Arai, Toshiyuki Iwamoto, Yuta Watanabe, Atsushi Murakoshi
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Patent number: 10438959Abstract: A semiconductor memory device includes a first electrode film and a second electrode film spreading along a first direction and a second direction, first insulating plates intermittently disposed along the first direction and each of two columns separated in the second direction from each other, second insulating plates provided between the two columns, intermittently disposed along the first direction and each of n columns, third insulating plates provided between one of the two columns and a column formed of the second insulating plates, intermittently disposed along the first direction, a first insulating member provided between the first insulating plate and the third insulating plate, and a second insulating member provided between the second insulating plate and the third insulating plate. The first electrode film is divided into two parts between the two columns. The second electrode film is divided into {(n+1)×2} parts between the two columns.Type: GrantFiled: June 19, 2018Date of Patent: October 8, 2019Assignee: Toshiba Memory CorporationInventors: Tatsuya Kato, Atsushi Murakoshi, Fumitaka Arai
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Publication number: 20190273092Abstract: A semiconductor storage device includes a semiconductor substrate and a plurality of first wiring layers stacked above the semiconductor substrate in a first direction orthogonal to the semiconductor substrate, and extending in a second direction intersecting the first direction and parallel to the semiconductor substrate. The device further includes a first memory pillar including a semiconductor layer and a first insulation layer extending in the first direction, the first insulation layer provided between the plurality of first wiring layers and the semiconductor layer so as to contact the semiconductor layer, and charge storage layers provided respectively between the plurality of first wiring layers and the first insulation layer. One or more of the charge storage layers is in contact with the first insulation layer. A plurality of second insulation layers is provided between each of the plurality of first wiring layers and each of the charge storage layers.Type: ApplicationFiled: August 27, 2018Publication date: September 5, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Hiroki SASAKI, Atsushi MURAKOSHI, Ryuji OHBA
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Publication number: 20190259774Abstract: A storage device includes: a plurality of electrode films stacked in a first direction, and extending in a second direction intersecting the first direction; a first semiconductor film provided adjacent to the plurality of electrode films, and extending in the first direction; a first charge holding film provided between one electrode film among the plurality of electrode films, and the semiconductor film, and including any one of a metal, a metal compound, and a high dielectric material; and a second semiconductor film located between the first semiconductor film and the charge holding film, and extending in the first direction along the first semiconductor film. The second semiconductor film is electrically insulated from the plurality of electrode films, the first charge holding film, and the first semiconductor film.Type: ApplicationFiled: September 6, 2018Publication date: August 22, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Atsushi MURAKOSHI, Hiroki SASAKI
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Patent number: 10276586Abstract: According to one embodiment, a semiconductor device includes a substrate and a semiconductor layer. The device further includes a first electrode layer that is provided on a side surface of the semiconductor layer with a first insulating film interposed therebetween. The device further includes a charge storage layer provided on a side surface of the first electrode layer with the second insulating film interposed therebetween.Type: GrantFiled: September 1, 2016Date of Patent: April 30, 2019Assignee: Toshiba Memory CorporationInventors: Atsushi Murakoshi, Yasuhito Yoshimizu, Tomofumi Inoue, Tatsuya Kato, Yuta Watanabe, Fumitaka Arai
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Publication number: 20180301461Abstract: A semiconductor memory device includes a first electrode film and a second electrode film spreading along a first direction and a second direction, first insulating plates intermittently disposed along the first direction and each of two columns separated in the second direction from each other, second insulating plates provided between the two columns, intermittently disposed along the first direction and each of n columns, third insulating plates provided between one of the two columns and a column formed of the second insulating plates, intermittently disposed along the first direction, a first insulating member provided between the first insulating plate and the third insulating plate, and a second insulating member provided between the second insulating plate and the third insulating plate. The first electrode film is divided into two parts between the two columns. The second electrode film is divided into {(n+1)×2} parts between the two columns.Type: ApplicationFiled: June 19, 2018Publication date: October 18, 2018Applicant: Toshiba Memory CorporationInventors: Tatsuya Kato, Atsushi Murakoshi, Fumitaka Arai
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Patent number: 10020315Abstract: A semiconductor memory device includes a first electrode film and a second electrode film spreading along a first direction and a second direction, first insulating plates intermittently disposed along the first direction and each of two columns separated in the second direction from each other, second insulating plates provided between the two columns, intermittently disposed along the first direction and each of n columns, third insulating plates provided between one of the two columns and a column formed of the second insulating plates, intermittently disposed along the first direction, a first insulating member provided between the first insulating plate and the third insulating plate, and a second insulating member provided between the second insulating plate and the third insulating plate. The first electrode film is divided into two parts between the two columns. The second electrode film is divided into {(n+1)×2} parts between the two columns.Type: GrantFiled: September 15, 2017Date of Patent: July 10, 2018Assignee: Toshiba Memory CorporationInventors: Tatsuya Kato, Atsushi Murakoshi, Fumitaka Arai
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Patent number: 9966381Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a first conductive film provided on a first region of the first insulating film, a second conductive film provided on a second region of the first insulating film, a first stacked body provided on the first conductive film, a second stacked body provided on the second conductive film, a first semiconductor pillar, and two conductive pillars. In the first stacked body, a second insulating film and an electrode film are stacked alternately. In the second stacked body, a third insulating film and a first film are stacked alternately. The two conductive pillars extend in the first direction through the second stacked body, are separated from the second conductive film, sandwich the second conductive film, and are connected at a bottom ends of the second conductive pillars to the semiconductor substrate.Type: GrantFiled: September 16, 2016Date of Patent: May 8, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Fumitaka Arai, Tatsuya Kato, Satoshi Nagashima, Katsuyuki Sekine, Yuta Watanabe, Keisuke Kikutani, Atsushi Murakoshi
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Patent number: 9847342Abstract: A semiconductor memory device includes a first structural body, a second structural body and interconnections. The first and the second structural bodies are separated in a first direction and extend in a second direction. The interconnections are provided between the first structural body and the second structural body, extend in the second direction, and are separated from each other along a third direction. The first and the second structural bodies each includes an insulating member, a column-shaped body and an insulating film. The insulating member and the column-shaped body are disposed in an alternating manner along the second direction and extend in the third direction. The insulating members of the first and second structural bodies make contact with the interconnections.Type: GrantFiled: September 16, 2016Date of Patent: December 19, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Satoshi Nagashima, Katsumi Yamamoto, Kohei Sakaike, Tatsuya Kato, Keisuke Kikutani, Fumitaka Arai, Atsushi Murakoshi, Shunichi Takeuchi, Katsuyuki Sekine
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Publication number: 20170271348Abstract: A semiconductor memory device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a first conductive film provided on a first region of the first insulating film, a second conductive film provided on a second region of the first insulating film, a first stacked body provided on the first conductive film, a second stacked body provided on the second conductive film, a first semiconductor pillar, and two conductive pillars. In the first stacked body, a second insulating film and an electrode film are stacked alternately. In the second stacked body, a third insulating film and a first film are stacked alternately. The two conductive pillars extend in the first direction through the second stacked body, are separated from the second conductive film, sandwich the second conductive film, and are connected at a bottom ends of the second conductive pillars to the semiconductor substrate.Type: ApplicationFiled: September 16, 2016Publication date: September 21, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Fumitaka ARAI, Tatsuya KATO, Satoshi NAGASHIMA, Katsuyuki SEKINE, Yuta WATANABE, Keisuke KIKUTANI, Atsushi MURAKOSHI
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Publication number: 20170263619Abstract: A semiconductor memory device includes a first structural body, a second structural body and interconnections. The first and the second structural bodies are separated in a first direction and extend in a second direction. The interconnections are provided between the first structural body and the second structural body, extend in the second direction, and are separated from each other along a third direction. The first and the second structural bodies each includes an insulating member, a column-shaped body and an insulating film. The insulating member and the column-shaped body are disposed in an alternating manner along the second direction and extend in the third direction. The insulating members of the first and second structural bodies make contact with the interconnections.Type: ApplicationFiled: September 16, 2016Publication date: September 14, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Satoshi NAGASHIMA, Katsumi YAMAMOTO, Kohei SAKAIKE, Tatsuya KATO, Keisuke KlKUTANI, Fumitaka ARAI, Atsushi MURAKOSHI, Shunichi TAKEUCHI, Katsuyuki SEKINE
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Publication number: 20170263613Abstract: According to one embodiment, a semiconductor device includes a substrate and a semiconductor layer. The device further includes a first electrode layer that is provided on a side surface of the semiconductor layer with a first insulating film interposed therebetween. The device further includes a charge storage layer provided on a side surface of the first electrode layer with the second insulating film interposed therebetween.Type: ApplicationFiled: September 1, 2016Publication date: September 14, 2017Inventors: Atsushi MURAKOSHI, Yasuhito YOSHIMIZU, Tomofumi INOUE, Tatsuya KATO, Yuta WATANABE, Fumitaka ARAI
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Publication number: 20170243945Abstract: In a semiconductor memory device, first insulating films are arranged along a first direction and a second direction and extend in a third direction. Interconnect is disposed between the first insulating films in the first direction and extends in the third direction. Electrodes are disposed between the first insulating films in the first direction on a second direction side of the interconnect, and is arranged along the third direction. Second insulating film is disposed between the interconnect and the electrodes. Semiconductor members are arranged along the third direction between the first insulating films in the second direction and extend in the first direction. The electrode is disposed between the interconnect and the semiconductor members. Third insulating film is disposed between the electrodes and the semiconductor member and is thicker than the second insulating film.Type: ApplicationFiled: September 13, 2016Publication date: August 24, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: KATSUYUKI SEKINE, TATSUYA KATO, FUMITAKA ARAI, TOSHIYUKI IWAMOTO, YUTA WATANABE, ATSUSHI MURAKOSHI
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Patent number: 9741730Abstract: According to one embodiment, the first separation film separates the control electrode, the first insulating layer, the charge storage layer, the intermediate insulating layer, the floating electrode layer, and the second insulating layer in a first direction. The second separation film separates a first stacked unit in a second direction. The first stacked unit includes the charge storage layer, the intermediate insulating layer, the floating electrode layer, the second insulating layer, and the semiconductor layer. The second direction intersects the first direction. The second separation film contains silicon.Type: GrantFiled: March 4, 2016Date of Patent: August 22, 2017Assignee: Toshiba Memory CorporationInventors: Atsushi Murakoshi, Kazuhito Furumoto
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Patent number: 9735167Abstract: A semiconductor memory device according to one embodiment, includes a plurality of first interconnects extending in a first direction and arrayed along a second direction crossing the first direction, a plurality of semiconductor pillars arrayed in a row along the first direction in each of spaces among the first interconnects and extending in a third direction crossing the first direction and the second direction, a first electrode disposed between one of the semiconductor pillars and one of the first interconnects, a first insulating film disposed between the first electrode and one of the first interconnects, a first insulating member disposed between the semiconductor pillars in the first direction and extending in the third direction and opposed the first interconnects not via the first insulating film.Type: GrantFiled: August 31, 2015Date of Patent: August 15, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuya Kato, Fumitaka Arai, Satoshi Nagashima, Katsuyuki Sekine, Yuta Watanabe, Keisuke Kikutani, Atsushi Murakoshi