Patents by Inventor Atsushi Murakoshi
Atsushi Murakoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7977141Abstract: A method of manufacturing a solid-state image pickup device according to an embodiment includes forming first and second holes in a semiconductor substrate, forming insulating films on surfaces of the first and second holes, forming a contact and an alignment mark by embedding a conducting material in the first and second holes, forming a photodiode in the semiconductor substrate, forming a wiring layer including a connecting part for connecting to the contact and a wiring for connecting to the connecting part, bonding a supporting substrate on the wiring layer, exposing the contact and the alignment mark on the surface of the semiconductor substrate by reducing the semiconductor substrate in thickness, and forming a filter and a lens on the photodiode based on the alignment mark.Type: GrantFiled: August 31, 2009Date of Patent: July 12, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Tsubasa Harada, Atsushi Murakoshi
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Patent number: 7928483Abstract: A hard mask material film is formed on a semiconductor substrate and a recess is formed immediately below an opening in an upper surface of the semiconductor substrate. Next, a p-type region is formed immediately below the recess by implanting impurities into an imaging region using the hard mask material film as a mask. Moreover, a trench is formed by further processing the recess in a processing region. A half-buried dielectric film and a STI are formed by burying a dielectric material in the recess and the trench to remove the hard mask material film. Next, two electrodes are formed so as to overlap the half-buried dielectric film and the STI, respectively, and impurities are implanted into the imaging region using one electrode and the half-buried dielectric film as a mask, and hence a n-type region constituting a photodiode is formed in a region being in contact with the p-type region in the semiconductor substrate.Type: GrantFiled: February 19, 2009Date of Patent: April 19, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Murakoshi, Katsunori Yahashi
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Publication number: 20110084350Abstract: According to one embodiment, a solid state image capture device includes a multilayered interconnect layer, a semiconductor substrate, a pillar diffusion layer and an insulating member. The multilayered interconnect layer includes an interconnect. The semiconductor substrate is provided on the multilayered interconnect layer and the semiconductor substrate has a through-trench. The pillar diffusion layer is formed in the semiconductor substrate around the through-trench. In addition, an insulating member is filled into the through-trench.Type: ApplicationFiled: July 2, 2010Publication date: April 14, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsushi MURAKOSHI, Tsubasa Harada
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Publication number: 20110079833Abstract: A hard mask material film is formed on a semiconductor substrate and a recess is formed immediately below an opening in an upper surface of the semiconductor substrate. Next, a p-type region is formed immediately below the recess by implanting impurities into an imaging region using the hard mask material film as a mask. Moreover, a trench is formed by further processing the recess in a processing region. A half-buried dielectric film and a STI are formed by burying a dielectric material in the recess and the trench to remove the hard mask material film. Next, two electrodes are formed so as to overlap the half-buried dielectric film and the STI, respectively, and impurities are implanted into the imaging region using one electrode and the half-buried dielectric film as a mask, and hence a n-type region constituting a photodiode is formed in a region being in contact with the p-type region in the semiconductor substrate.Type: ApplicationFiled: December 8, 2010Publication date: April 7, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Atsushi Murakoshi, Katsunori Yahashi
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Publication number: 20110031576Abstract: A solid-state imaging device includes a first-conductive semiconductor layer, a second-conductive semiconductor layer that is provided on the first-conductive semiconductor layer, a light receiving element that is formed in the second-conductive semiconductor layer, and an element isolation region that is formed to surround the light receiving element in an in-plane direction of the second-conductive semiconductor layer, in which the element isolation region includes a first-conductive first element isolation unit that is connected to the first-conductive semiconductor layer, a hollow that is formed on the first-conductive first element isolation unit, and a first-conductive second element isolation unit that is formed on the hollow.Type: ApplicationFiled: March 12, 2010Publication date: February 10, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Seiichi Iwasa, Yoshio Kasai, Takeshi Yousyou, Tsutomu Sato, Atsushi Murakoshi
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Publication number: 20100237451Abstract: In a back-illuminated solid-state imaging device, a multilayer interconnect layer, a semiconductor substrate, a plurality of color filters, and a plurality of microlenses are provided in this order. A p-type region is formed so as to partition a lower portion of the semiconductor substrate into a plurality of regions, and an insulating member illustratively made of BSG is buried immediately above the p-type region. PD regions are isolated from each other by the p-type region and the insulating member. Moreover, a high-concentration region is formed in a lower portion of the PD region, and an upper portion is served as a low-concentration region.Type: ApplicationFiled: September 10, 2009Publication date: September 23, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Atsushi Murakoshi
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Patent number: 7772641Abstract: A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.Type: GrantFiled: March 6, 2007Date of Patent: August 10, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Ichiro Omura, Yoko Sakiyama, Hideki Nozaki, Atsushi Murakoshi, Masanobu Tsuchitani, Koichi Sugiyama, Tsuneo Ogura, Masakazu Yamaguchi, Tatsuo Naijo
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Publication number: 20100181637Abstract: A method of manufacturing a solid-state image pickup device according to an embodiment includes forming first and second holes in a semiconductor substrate, forming insulating films on surfaces of the first and second holes, forming a contact and an alignment mark by embedding a conducting material in the first and second holes, forming a photodiode in the semiconductor substrate, forming a wiring layer including a connecting part for connecting to the contact and a wiring for connecting to the connecting part, bonding a supporting substrate on the wiring layer, exposing the contact and the alignment mark on the surface of the semiconductor substrate by reducing the semiconductor substrate in thickness, and forming a filter and a lens on the photodiode based on the alignment mark.Type: ApplicationFiled: August 31, 2009Publication date: July 22, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsubasa Harada, Atsushi Murakoshi
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Publication number: 20090212337Abstract: A hard mask material film is formed on a semiconductor substrate and a recess is formed immediately below an opening in an upper surface of the semiconductor substrate. Next, a p-type region is formed immediately below the recess by implanting impurities into an imaging region using the hard mask material film as a mask. Moreover, a trench is formed by further processing the recess in a processing region. A half-buried dielectric film and a STI are formed by burying a dielectric material in the recess and the trench to remove the hard mask material film. Next, two electrodes are formed so as to overlap the half-buried dielectric film and the STI, respectively, and impurities are implanted into the imaging region using one electrode and the half-buried dielectric film as a mask, and hence a n-type region constituting a photodiode is formed in a region being in contact with the p-type region in the semiconductor substrate.Type: ApplicationFiled: February 19, 2009Publication date: August 27, 2009Inventors: Atsushi MURAKOSHI, Katsunori Yahashi
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Publication number: 20080230801Abstract: A method for manufacturing a trench type power semiconductor device is provided. The method includes: forming a first silicon oxide film on a silicon substrate; forming a thermal oxidation-resistant film on the first silicon oxide film; forming an opening in the first silicon oxide film and the thermal oxidation-resistant film; forming a sidewall on an inner side surface of the opening; forming a trench in the silicon substrate by etching the silicon substrate using the first silicon oxide film, the thermal oxidation-resistant film, and the sidewall as a mask; removing the sidewall; forming a second silicon oxide film thicker than the first silicon oxide film on an inner surface of the trench by applying thermal oxidation to the silicon substrate; burying a trench gate electrode in the trench; removing the thermal oxidation-resistant film; and introducing impurities into at least part of a region of the silicon substrate between the trenches.Type: ApplicationFiled: March 18, 2008Publication date: September 25, 2008Inventors: Atsushi MURAKOSHI, Noboru MATSUDA
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Publication number: 20070210350Abstract: A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.Type: ApplicationFiled: March 6, 2007Publication date: September 13, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ichiro Omura, Yoko Sakiyama, Hideki Nozaki, Atsushi Murakoshi, Masanobu Tsuchitani, Koichi Sugiyama, Tsuneo Ogura, Masakazu Yamaguchi, Tatsuo Naijo
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Patent number: 7145658Abstract: An apparatus for evaluating semiconductor material having a pump laser configured to irradiate a pump beam modulated at a modulation frequency on a semiconductor wafer, a probe laser configured to irradiate a probe beam on the semiconductor wafer, and a detector configured to detect a reflection of the probe beam from the semiconductor wafer.Type: GrantFiled: August 7, 2003Date of Patent: December 5, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Haruko Akutsu, Katsumi Rikimaru, Kyoichi Suguro, Tatsuya Shima, Yoshimasa Kawase, Atsushi Murakoshi
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Patent number: 6939787Abstract: The semiconductor device comprises a pair of impurity diffused regions formed in a silicon substrate 10, spaced from each other, and a gate electrode 26 formed above the silicon substrate 10 between the pair of impurity diffused regions 38 intervening a gate insulation film 12 therebetween. The gate electrode 26 is formed of a polycrystalline silicon film 16 formed on the gate insulation film 12, a polycrystalline silicon film 30 formed on the polycrystalline silicon film 16 and having crystal grain boundaries discontinuous to the polycrystalline silicon film 16, a metal nitride film 20 formed on the polycrystalline silicon film 30, and a metal film 22 formed on the barrier metal film 20. Whereby diffusion of the boron from the first polycrystalline silicon film 16 toward the metal nitride film 20 can be decreased. Thus, depletion of the gate electrode 26 can be suppressed.Type: GrantFiled: October 13, 2004Date of Patent: September 6, 2005Assignees: Fujitsu Limited, Kabushiki Kaisha ToshibaInventors: Fumio Ohtake, Yasushi Akasaka, Atsushi Murakoshi, Kyoichi Suguro
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Patent number: 6875986Abstract: According to the ion generation method, ion source material composed of an element of desired ions to be generated and I is heated so that vapor of the compound is generated, and the ions are generated by discharging the vapor. The iodide has no corrosiveness, and can be stably ionized. Further, it hardly reacts with oxygen or water and is safe.Type: GrantFiled: April 27, 2000Date of Patent: April 5, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Murakoshi, Kyoichi Suguro, Katsuya Okumura
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Publication number: 20050062115Abstract: The semiconductor device comprises a pair of impurity diffused regions formed in a silicon substrate 10, spaced from each other, and a gate electrode 26 formed above the silicon substrate 10 between the pair of impurity diffused regions 38 intervening a gate insulation film 12 therebetween. The gate electrode 26 is formed of a polycrystalline silicon film 16 formed on the gate insulation film 12, a polycrystalline silicon film 30 formed on the polycrystalline silicon film 16 and having crystal grain boundaries discontinuous to the polycrystalline silicon film 16, a metal nitride film 20 formed on the polycrystalline silicon film 30, and a metal film 22 formed on the barrier metal film 20. Whereby diffusion of the boron from the first polycrystalline silicon film 16 toward the metal nitride film 20 can be decreased. Thus, depletion of the gate electrode 26 can be suppressed.Type: ApplicationFiled: October 13, 2004Publication date: March 24, 2005Applicants: FUJITSU LIMITED, KABUSHIKI KAISHA TOSHIBAInventors: Fumio Ohtake, Yasushi Akasaka, Atsushi Murakoshi, Kyoichi Suguro
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Publication number: 20040196464Abstract: An apparatus for evaluating semiconductor material having a pump laser configured to irradiate a pump beam modulated at a modulation frequency on a semiconductor wafer, a probe laser configured to irradiate a probe beam on the semiconductor wafer, and a detector configured to detect a reflection of the probe beam from the semiconductor wafer.Type: ApplicationFiled: August 7, 2003Publication date: October 7, 2004Inventors: Haruko Akutsu, Katsumi Rikimaru, Kyoichi Suguro, Tatsuya Shima, Yoshimasa Kawase, Atsushi Murakoshi
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Patent number: 6693023Abstract: In an ion implantation method using an ion implantation equipment having an extraction electrode and a post accelerator, ion is uniformly implanted into a shallow region from the surface of a sample by setting an applied volt. of the post accelerator higher than an applied volt. of the extraction electrode.Type: GrantFiled: February 22, 2002Date of Patent: February 17, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Murakoshi, Kyoichi Suguro
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Patent number: 6646268Abstract: According to the ion generation method, ion source material composed of an element of desired ions to be generated and I is heated so that vapor of the compound is generated, and the ions are generated by discharging the vapor. The iodide has no corrosiveness, and can be stably ionized. Further, it hardly reacts with oxygen or water and is safe.Type: GrantFiled: February 27, 2002Date of Patent: November 11, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Murakoshi, Kyoichi Suguro, Katsuya Okumura
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Publication number: 20030171859Abstract: According to the present invention, there is disclosed a car performance addition service providing system in which a predetermined setting division provides an addition service relating to a performance to a car using an electronic control via communication, the system comprising a first transmission unit which transmits setting information relating to the performance to the car, an acceptance unit which accepts a request for desired performance setting from the car in accordance with the setting information transmitted by the first transmission unit, and a second transmission unit which transmits setting data corresponding to the request accepted by the acceptance unit to the car.Type: ApplicationFiled: March 28, 2003Publication date: September 11, 2003Inventor: Atsushi Murakoshi
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Patent number: 6614033Abstract: An electrically conductive mask having openings formed is located above a semiconductor substrate and ions are implanted into the surface of the semiconductor substrate through the electrically conductive mask, thereby forming ion implanted layers. For ion implantation under different conditions, a dedicated electrically conductive mask is used with each ion implantation step.Type: GrantFiled: December 5, 2001Date of Patent: September 2, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Kyoichi Suguro, Atsushi Murakoshi, Katsuya Okumura