Abstract: A semiconductor device is fabricated by a method comprising the steps of: selectively introducing a halogen element or argon into a device region 14 of a silicon substrate 10; and wet oxidizing the silicon substrate 10 in an ambient atmosphere which an H2O partial pressure is less than 1 atm to thereby form a silicon oxide film 22 in the device region 14 of the silicon substrate 10, and a silicon oxide film 24 thinner than the silicon oxide film 22 in a device region 16 of the silicon substrate 10. Whereby the silicon oxide film in a device region 14 with the halogen element or argon introduced can be selectively formed thick. The silicon oxide films are formed by the wet oxidation, whereby the gate insulation films can be more reliable than those formed by the dry oxidation.

Abstract: Claimed and disclosed is a method of manufacturing a semiconductor device, the method comprising the steps of forming a dummy gate on a semiconductor substrate, forming a source-drain diffusion region by introducing an impurity into the semiconductor substrate having the dummy gate as a mask, removing the dummy gate to form an opening, and forming a gate electrode within the opening with a gate insulating film formed below the gate electrode. The dummy gate is further formed by coating the semiconductor substrate with a polymer having a higher carbon content than hydrogen content so as to form a polymer film, forming a photoresist pattern on the polymer film, and transferring the pattern shape of the photoresist pattern onto the polymer film.

Abstract: In an ion implantation method using an ion implantation equipment having an extraction electrode and a post accelerator, ion is uniformly implanted into a shallow region from the surface of a sample by setting an applied volt. of the post accelerator higher than an applied volt. of the extraction electrode.

Abstract: According to the ion generation method, ion source material composed of an element of desired ions to be generated and I is heated so that vapor of the compound is generated, and the ions are generated by discharging the vapor. The iodide has no corrosiveness, and can be stably ionized. Further, it hardly reacts with oxygen or water and is safe.

Abstract: In an ion implantation method using an ion implantation equipment having an extraction electrode and a post accelerator, ion is uniformly implanted into a shallow region from the surface of a sample by setting an applied volt. of the post accelerator higher than an applied volt. of the extraction electrode.

Abstract: The semiconductor device comprises a pair of impurity diffused regions formed in a silicon substrate 10, spaced from each other, and a gate electrode 26 formed above the silicon substrate 10 between the pair of impurity diffused regions 38 intervening a gate insulation film 12 therebetween. The gate electrode 26 is formed of a polycrystalline silicon film 16 formed on the gate insulation film 12, a polycrystalline silicon film 30 formed on the polycrystalline silicon film 16 and having crystal grain boundaries discontinuous to the polycrystalline silicon film 16, a metal nitride film 20 formed on the polycrystalline silicon film 30, and a metal film 22 formed on the barrier metal film 20. Whereby diffusion of the boron from the first polycrystalline silicon film 16 toward the metal nitride film 20 can be decreased. Thus, depletion of the gate electrode 26 can be suppressed.

Abstract: An electrically conductive mask having openings formed is located above a semiconductor substrate and ions are implanted into the surface of the semiconductor substrate through the electrically conductive mask, thereby forming ion implanted layers. For ion implantation under different conditions, a dedicated electrically conductive mask is used with each ion implantation step.

Abstract: Disclosed is a semiconductor device having an N-type MIS transistor formed in a first region and a P-type MIS transistor formed in a second region, wherein, the N-type MIS transistor includes a first gate insulating film formed on at least the bottom of a first concave portion formed in the first region and a first gate electrode formed on the first gate insulating film, the P-type MIS transistor includes a second gate insulating film formed on at least the bottom of a second concave portion formed in the second region and a second gate electrode formed on the second gate insulating film, each of the first and second gate electrodes includes at least one metal-containing film, and at least one of the first and second gate electrodes is of a laminate structure including a plurality of the metal-containing films, and the work function of the metal-containing film constituting at least a part of the first gate electrode and in contact with the first gate insulating film is smaller than the work function of the m

Abstract: An electrically conductive mask having openings formed is located above a semiconductor substrate and ions are implanted into the surface of the semiconductor substrate through the electrically conductive mask, thereby forming ion implanted layers. For ion implantation under different conditions, a dedicated electrically conductive mask is used wit each ion implantation step.

Abstract: A semiconductor device is fabricated by a method comprising the steps of: selectively introducing a halogen element or argon into a device region 14 of a silicon substrate 10; and wet oxidizing the silicon substrate 10 in an ambient atmosphere which an H2O partial pressure is less than 1 atm to thereby form a silicon oxide film 22 in the device region 14 of the silicon substrate 10, and a silicon oxide film 24 thinner than the silicon oxide film 22 in a device region 16 of the silicon substrate 10. Whereby the silicon oxide film in a device region 14 with the halogen element or argon introduced can be selectively formed thick. The silicon oxide films are formed by the wet oxidation, whereby the gate insulation films can be more reliable than those formed by the dry oxidation.

Abstract: An impurity diffusion surface layer is formed in a surface of a silicon substrate, and an aluminum electrode is arranged in direct contact with the impurity diffusion layer. The surface layer contains Ge as an impurity serving to change the lattice constant in a concentration of at least 1.times.10.sup.21 cm.sup.-3 under a thermal non-equilibrium state. The lattice constant of the surface layer is set higher than that of silicon containing the same concentration of germanium under a thermal equilibrium state. As a result, it is possible to decrease the Schittky barrier height at the contact between the surface layer and the electrode. The surface layer also contains an electrically active boron as an impurity serving to impart carriers in a concentration higher than the critical concentration of solid solution in silicon under a thermal equilibrium state. The presence of Ge permits the carrier mobility within the surface layer higher than that within silicon.

Abstract: A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed.

Abstract: An impurity diffusion surface layer is formed in a surface of a silicon substrate, and an aluminum electrode is arranged in direct contact with the impurity diffusion layer. The surface layer contains Ge as an impurity serving to change the lattice constant in a concentration of at least 1.times.10.sup.21 cm.sup.-1 under a thermal non-equilibrium state. The lattice constant of the surface layer is set higher than that of silicon containing the same concentration of germanium under a thermal equilibrium state. As a result, it is possible to decrease the Schittky barrier height at the contact between the surface layer and the electrode. The surface layer also contains an electrically active boron as an impurity serving to impart carriers in a concentration higher than the critical concentration of solid solution in silicon under a thermal equilibrium state. The presence of Ge permits the carrier mobility within the surface layer higher than that within silicon.

Abstract: An ion generation device includes a chamber in which plasma is generated, a first opening for introducing gas to be ionized by the plasma, and a second opening for irradiating ions generated from the gas. The inner wall of the chamber is coated with metal which is resistant to chemical etching by the ions and radicals.

Abstract: An ion generation device includes a chamber in which plasma is generated, a first opening for introducing gas to be ionized by the plasma, and a second opening for irradiating ions generated from the gas. The inner wall of the chamber is coated with metal which is resistant to chemical etching by the ions and radicals.

Abstract: An impurity diffusion layer shallow in diffusion depth and high in activity is formed in a semiconductor device. In the semiconductor device, clusters of icosahedron structure each composed of boron atoms are formed in the silicon crystal of the impurity layer of the semiconductor device so as to function as acceptors. Further, after the clusters of icosahedron structure each composed of 12 boron atoms have been formed by implanting boron ions at high concentration, the device is processed at temperature lower than 700.degree. C. to prevent the boron from being decreased due to combination with silicon. Since an impurity layer shallow in diffusion from the substrate surface and high in activity can be formed and further the clusters of icosahedron structure each composed of 12 boron atoms can be utilized as acceptors, it is possible to realize a high doping even in the manufacturing process for the devices not suitable for high temperature annealing.

Abstract: An impurity diffusion layer shallow in diffusion depth and high in activity is formed in a semiconductor device. In the semiconductor device, clusters of icosahedron structure each composed of boron atoms are formed in the silicon crystal of the impurity layer of the semiconductor device so as to function as acceptors. Further, after the clusters of icosahedron structure each composed of 12 boron atoms have been formed by implanting boron ions at high concentration, the device is processed at temperature lower than 700.degree. C. to prevent the boron from being decreased due to combination with silicon. Since an impurity layer shallow in diffusion from the substrate surface and high in activity can be formed and further the clusters of icosahedron structure each composed of 12 boron atoms can be utilized as acceptors, it is possible to realize a high doping even in the manufacturing process for the devices not suitable for high temperature annealing.