Patents by Inventor Atsushi Ogasawara
Atsushi Ogasawara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240087073Abstract: A control device reads power consumption, information on the delivery number and weight of a first product set, and information on the delivery number and weight of a second product set from a storage device. The control device proportionally divides the power consumption. The control device reads a first conversion formula from the storage device, and calculates CO2 emissions from transportation of the first product set from an A station to a B station and CO2 emissions from transportation of the second product set from the A station to the B station by substituting the power consumptions, into the first conversion formula.Type: ApplicationFiled: July 10, 2023Publication date: March 14, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Atsushi KOMADA, Mitsuru OGASAWARA, Masahiko ISHII, Hidetaka ASANO, Tomokazu ISHII, Koji HETSUGI, Kosuke YONEKAWA, Yoshikazu JIKUHARA
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Publication number: 20240078500Abstract: A management device includes a communication device and a control device. The communication device is configured to communicate with a moving object configured to transport a product from an upstream company to a downstream company. The control device is configured to calculate CO2 emissions emitted by transportation of the product based on an amount of energy consumed by the moving object from a transportation start time point to a transportation completion time point of the product.Type: ApplicationFiled: August 11, 2023Publication date: March 7, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Atsushi KOMADA, Mitsuru OGASAWARA, Masahiko ISHII, Hidetaka ASANO, Tomokazu ISHII, Koji HETSUGI, Kosuke YONEKAWA, Yoshikazu JIKUHARA
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Publication number: 20240079200Abstract: A multi-electron beam image acquiring apparatus includes a stage configured to mount thereon a substrate, an illumination optical system configured to apply multiple primary electron beams to the substrate, a plurality of multipole lenses including at least two stages of multipole lenses, arranged at positions common to a trajectory of the multiple primary electron beams and a trajectory of multiple secondary electron beams which are emitted because the substrate is irradiated with the multiple primary electron beams and each configured to include at least four electrodes and at least four magnetic poles, and a multi-detector configured to detect the multiple secondary electron beams separated from the trajectory of the multiple primary electron beams, wherein one of the plurality of multipole lenses separates the multiple secondary electron beams from the trajectory of the multiple primary electron beams.Type: ApplicationFiled: November 9, 2023Publication date: March 7, 2024Applicant: NuFlare Technology, Inc.Inventors: Kazuhiko INOUE, Atsushi ANDO, Munehiro OGASAWARA
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Publication number: 20240069506Abstract: A management method for managing a CO2 emission amount to be emitted by producing a product, includes: reading out a first CO2 emission amount that is a CO2 emission amount per unit weight of a first raw material and a second CO2 emission amount that is a CO2 emission amount per unit weight of a second raw material; and calculating the CO2 emission amount of the product based on a CO2 emission amount to be calculated from the first CO2 emission amount and from a weight of the first raw material used to produce the product, and a CO2 emission amount to be calculated from the second CO2 emission amount and from a weight of the second raw material used to produce the product.Type: ApplicationFiled: August 7, 2023Publication date: February 29, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Atsushi KOMADA, Mitsuru OGASAWARA, Masahiko ISHII, Hidetaka ASANO, Tomokazu ISHII, Koji HETSUGI, Kosuke YONEKAWA, Yoshikazu JIKUHARA
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Publication number: 20240069533Abstract: A management method for management of a CO2 emission amount emitted by production of a product in a production line where a first product and a second product are produced includes acquiring a power consumption amount consumed in the production line for a predetermined period, and calculating a CO2 emission amount for each product by allocating the power consumption amount based on a ratio of a total work time required to produce the first product in the production line during the predetermined period and a total work time required to produce the second product in the production line during the predetermined period.Type: ApplicationFiled: August 3, 2023Publication date: February 29, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Atsushi KOMADA, Mitsuru OGASAWARA, Masahiko ISHII, Hidetaka ASANO, Tomokazu ISHII, Koji HETSUGI, Kosuke YONEKAWA, Yoshikazu JIKUHARA
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Publication number: 20230105626Abstract: The semiconductor device includes a mesa diode structure(20) and a protective layer(17b). The mesa diode structure includes, from bottom to top, a P-type semiconductor layer(11), a first N-type semiconductor layer(12), and a second N-type semiconductor layer(13) having a higher impurity concentration than the first N-type semiconductor layer. The protective layer is arranged on a side wall around the mesa diode structure seen in a plane. Specifically, the protective layer is arranged on an upper side surface(11c) of the P-type semiconductor layer and on side surfaces(12a,13a) of the first N-type semiconductor layer and the second N-type semiconductor layer, but is not arranged on a lower side surface of the P-type semiconductor layer. A bevel angle(30) of a PN junction plane between the P-type semiconductor layer and the first N-type semiconductor layer to the upper side surface of the P-type semiconductor layer is set to 85 to 120 degrees.Type: ApplicationFiled: April 27, 2022Publication date: April 6, 2023Inventors: Koji ITO, Atsushi OGASAWARA, Ryota MURAI
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Patent number: 10707302Abstract: A semiconductor device manufacturing method includes: a pretreatment step of performing a hydrophobic treatment on a first exposed region of an exposed surface, an n-type semiconductor layer being exposed from the first exposed region, and a pn junction being exposed from the exposed surface; an impurity supplying step of supplying an n-type impurity to the first exposed region; a channel stopper forming step of irradiating the first exposed region with a laser beam to introduce the n-type impurity into the n-type semiconductor layer, thus forming a channel stopper; and a glass layer forming step of forming a glass layer using a glass composition so as to cover the exposed surface.Type: GrantFiled: November 25, 2016Date of Patent: July 7, 2020Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Atsushi Ogasawara, Fumihiro Homma
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Publication number: 20200083321Abstract: A semiconductor device manufacturing method includes: a pretreatment step of performing a hydrophobic treatment on a first exposed region of an exposed surface, an n-type semiconductor layer being exposed from the first exposed region, and a pn junction being exposed from the exposed surface; an impurity supplying step of supplying an n-type impurity to the first exposed region; a channel stopper forming step of irradiating the first exposed region with a laser beam to introduce the n-type impurity into the n-type semiconductor layer, thus forming a channel stopper; and a glass layer forming step of forming a glass layer using a glass composition so as to cover the exposed surface.Type: ApplicationFiled: November 25, 2016Publication date: March 12, 2020Inventors: Atsushi OGASAWARA, Fumihiro HOMMA
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Patent number: 10186425Abstract: In a method of manufacturing a semiconductor device having an oxide film removing step where an oxide film formed on a surface of a semiconductor substrate is partially removed, the oxide film removing step includes: a first step where a resist glass layer is selectively formed on an upper surface of the oxide film without using an exposure step; a second step where the resist glass layer is densified by baking the resist glass layer; and a third step where the oxide film is partially removed using the resist glass layer as a mask, wherein the resist glass layer is made of resist glass which contains at least SiO2, B2O3, Al2O3, and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na, K, and Zn.Type: GrantFiled: October 31, 2014Date of Patent: January 22, 2019Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventor: Atsushi Ogasawara
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Patent number: 9978882Abstract: Provided is a method of manufacturing a semiconductor device according to the present invention, a ring-shaped electrode plate 18 with an opening having a diameter smaller than a diameter of a semiconductor wafer W is disposed between a first electrode plate 14 and a second electrode plate 16, the semiconductor wafer W is arranged between the ring-shaped electrode plate 18 and the second electrode plate 16, and a glass film is formed on a glass film forming scheduled surface in a state where a potential lower than a potential V2 of the second electrode plate 16 is applied to the ring-shaped electrode plate 18.Type: GrantFiled: November 13, 2014Date of Patent: May 22, 2018Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Shinichi Nagase, Atsushi Ogasawara, Koji Ito
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Patent number: 9960228Abstract: A wide gap semiconductor device comprises a first conductive-type semiconductor layer (32); a second conductive-type region (41), (42) that is provided on the first conductive-type semiconductor layer (32); a first electrode (1), of which a part is disposed on the second conductive-type region (41), (42) and the other part is disposed on the first conductive-type semiconductor layer (32); an insulating layer (51), (52), (53) that is provided adjacent to the first electrode (10) on the first conductive-type semiconductor layer (32) and that extends to an end part of the wide gap semiconductor device; and a second electrode (20) that is provided between the first electrode (10) and the end part of the wide gap semiconductor device and that forms a schottky junction with the first conductive-type semiconductor layer (32).Type: GrantFiled: August 27, 2015Date of Patent: May 1, 2018Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Yusuke Maeyama, Shunichi Nakamura, Atsushi Ogasawara, Ryohei Osawa, Akihiko Shibukawa
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Patent number: 9941112Abstract: Provided is a method of manufacturing a semiconductor device which includes, in the following order: a first step of preparing a semiconductor element which includes a pn junction exposure portion; a second step of forming an insulation layer such that the insulation layer covers the pn junction exposure portion; and a third step of forming a glass layer on the insulation layer where a layer made of glass composition for protecting a semiconductor junction is formed on the insulation layer and, thereafter, the layer made of glass composition for protecting a semiconductor junction is baked.Type: GrantFiled: November 28, 2012Date of Patent: April 10, 2018Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTDInventors: Atsushi Ogasawara, Koji Ito, Kazuhiko Ito, Koya Muyari
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Publication number: 20170323791Abstract: In a method of manufacturing a semiconductor device having an oxide film removing step where an oxide film formed on a surface of a semiconductor substrate is partially removed, the oxide film removing step includes: a first step where a resist glass layer is selectively formed on an upper surface of the oxide film without using an exposure step; a second step where the resist glass layer is densified by baking the resist glass layer; and a third step where the oxide film is partially removed using the resist glass layer as a mask, wherein the resist glass layer is made of resist glass which contains at least SiO2, B2O3, Al2O3, and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na, K, and Zn.Type: ApplicationFiled: October 31, 2014Publication date: November 9, 2017Inventor: Atsushi OGASAWARA
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Publication number: 20170263697Abstract: A wide gap semiconductor device comprises a first conductive-type semiconductor layer (32); a second conductive-type region (41), (42) that is provided on the first conductive-type semiconductor layer (32); a first electrode (1), of which a part is disposed on the second conductive-type region (41), (42) and the other part is disposed on the first conductive-type semiconductor layer (32); an insulating layer (51), (52), (53) that is provided adjacent to the first electrode (10) on the first conductive-type semiconductor layer (32) and that extends to an end part of the wide gap semiconductor device; and a second electrode (20) that is provided between the first electrode (10) and the end part of the wide gap semiconductor device and that forms a schottky junction with the first conductive-type semiconductor layer (32).Type: ApplicationFiled: August 27, 2015Publication date: September 14, 2017Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Yusuke MAEYAMA, Shunichi NAKAMURA, Atsushi OGASAWARA, Ryohei OSAWA, Akihiko SHIBUKAWA
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Patent number: 9698069Abstract: Provided is a glass composition for protecting a semiconductor junction which contains at least SiO2, B2O3, Al2O3, ZnO and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K, wherein an average linear expansion coefficient within a temperature range of 50° C. to 550° C. falls within a range of 3.33×10?6 to 4.13×10?6. A semiconductor device having high breakdown strength can be manufactured using such a glass material containing no lead in the same manner as a conventional case where “a glass material containing lead silicate as a main component” is used.Type: GrantFiled: March 7, 2016Date of Patent: July 4, 2017Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Koya Muyari, Koji Ito, Atsushi Ogasawara, Kazuhiko Ito
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Patent number: 9570408Abstract: A resin-sealed semiconductor device 10 of the present invention includes: a mesa-type semiconductor element 100 which includes a mesa-type semiconductor base body having a pn-junction exposure portion in an outer peripheral tapered region which surrounds a mesa region, and a glass layer which covers at least the outer peripheral tapered region; and a molding resin 40 which seals the mesa-type semiconductor element 100, wherein the mesa-type semiconductor element 100 includes a glass layer which substantially contains no Pb as the glass layer. The resin-sealed semiconductor device of the present invention can acquire higher resistance to a reverse bias at a high temperature than a conventional resin-sealed semiconductor device, although the resin-sealed semiconductor device of the present invention has the structure where the mesa-type semiconductor element is molded with a resin in the same manner as the conventional resin-sealed semiconductor device.Type: GrantFiled: May 8, 2012Date of Patent: February 14, 2017Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Atsushi Ogasawara, Koji Ito, Kazuhiko Ito, Koya Muyari
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Publication number: 20160322512Abstract: Provided is a method of manufacturing a semiconductor device according to the present invention, a ring-shaped electrode plate 18 with an opening having a diameter smaller than a diameter of a semiconductor wafer W is disposed between a first electrode plate 14 and a second electrode plate 16, the semiconductor wafer W is arranged between the ring-shaped electrode plate 18 and the second electrode plate 16, and a glass film is formed on a glass film forming scheduled surface in a state where a potential lower than a potential V2 of the second electrode plate 16 is applied to the ring-shaped electrode plate 18.Type: ApplicationFiled: November 13, 2014Publication date: November 3, 2016Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Shinichi Nagase, Atsushi Ogasawara, Koji Ito
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Patent number: 9455231Abstract: A resin-sealed semiconductor device includes a mesa-type semiconductor element which includes a mesa-type semiconductor base body having a pn junction exposure portion in an outer peripheral tapered region surrounding a mesa region, and a glass layer which covers at least the outer peripheral tapered region; and a molding resin which seals the mesa-type semiconductor element, wherein the glass layer is formed by forming a layer made of a predetermined glass composition for protecting a semiconductor junction which substantially contains no Pb such that the layer covers the outer peripheral tapered region and, subsequently, by baking the layer made of the glass composition for protecting a semiconductor junction.Type: GrantFiled: April 16, 2013Date of Patent: September 27, 2016Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.Inventors: Atsushi Ogasawara, Koji Ito, Kazuhiko Ito, Koya Muyari
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Patent number: 9408307Abstract: A device housing package includes a substrate in a form of a rectangle, having a mounting region of a device at an upper surface thereof; a frame body disposed on the substrate so as to extend along an outer periphery of the mounting region, the frame body having a cutout formed at a part thereof; and an input-output terminal disposed in the cutout. The input-output terminal includes a first insulating layer, a second insulating layer overlaid on the first insulating layer, and a third insulating layer overlaid on the second insulating layer. First terminals set at a predetermined potential are disposed on an upper surface of the first insulating layer. Second terminals set at a predetermined potential are disposed on a lower surface of the first insulating layer. Third terminals through which AC signals flow are disposed on an upper surface of the second insulating layer.Type: GrantFiled: March 5, 2013Date of Patent: August 2, 2016Assignee: Kyocera CorporationInventors: Mahiro Tsujino, Eiichi Katayama, Emi Mukai, Atsushi Ogasawara
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Publication number: 20160190026Abstract: Provided is a glass composition for protecting a semiconductor junction which contains at least SiC2, B2O3, Al2O3, ZnO and at least two oxides of alkaline earth metals selected from a group consisting of CaO, MgO and BaO, and substantially contains none of Pb, As, Sb, Li, Na and K, wherein an average linear expansion coefficient within a temperature range of 50° C. to 550° C. falls within a range of 3.33×10?6 to 4.13×10?6. A semiconductor device having high breakdown strength can be manufactured using such a glass material containing no lead in the same manner as a conventional case where “a glass material containing lead silicate as a main component” is used.Type: ApplicationFiled: March 7, 2016Publication date: June 30, 2016Inventors: Koya MUYARI, Koji ITO, Atsushi OGASAWARA, Kazuhiko ITO