Abstract: A semiconductor device includes a backside power rail, a backside ground rail, and a backside isolation rail between the backside power rail and the backside ground rail. The backside isolation rail may provide adequate electrical isolation between the backside power rail and the backside ground rail, thereby enabling the backside power rail and the backside ground rail to be located relatively near to one another. The backside isolation rail may also cure actual electrical shorts between the backside power rail and the backside ground rail.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes a substrate extending along a first direction to define a length, a second direction orthogonal to the first direction to define a width, and a third direction orthogonal to the first and second direction to define a height. The substrate includes a first capacitance region and a second capacitance region. The first capacitance region has a first maximum operating voltage (Vmax) and the second capacitance region has a second Vmax that is greater than the first Vmax.

Abstract: A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dielectric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.

Abstract: A Resistive Random-Access Memory (RRAM) has an internal electrode; a high k dielectric layer surrounding and in contact with the internal electrode; a lower substrate; and a trench having three or more trench sides disposed within the lower substrate; and one or more interconnects each with an interconnect side. The interconnect side forms part of one of the trench sides. The internal electrode and the high k dielectric layer are disposed within the trench with the interconnect side in contact with the high k dielectric layer. In some embodiments, an external electrode is between and electrically connected to the high k dielectric layer and the internal electrode. The external electrode then forms the electrical connection between the high k dielectric and the interconnect side. Multiple embodiments are disclosed including RRAMs created in multiple substrates; different RRAM configurations; and dual, three-wire RRAMs with two interconnects. Arrays of RRAMs and methods of making are also disclosed.

Abstract: Embodiments of present invention provide a resistor structure. The resistor structure includes a first layer of electrically insulating material; and a second layer of resistive material directly adjacent to the first layer, wherein thermal conductivity of the first layer is equal to or larger than 100 W/m/K. In one embodiment, the first layer of electrically insulating material has a band gap equal to or larger than 4 eV and is selected from a group consisting of aluminum-nitride (AlN), boron-nitride (BN), and diamond (C).

Abstract: Embodiments of the present invention are directed to methods and resulting structures for integrated circuits having metal-insulator-metal (MIM) capacitors that serve as both decoupling capacitors and crack stops. In a non-limiting embodiment, an interconnect is formed on a first portion of a substrate in an interior region of the integrated circuit. A second portion of the substrate is exposed in an edge region of the integrated circuit. A MIM capacitor is formed over the second portion of the substrate in the edge region. The MIM capacitor includes two or more plates and one or more dielectric layers. Each dielectric layer is positioned between an adjacent pair of the two or more plates and a portion of the two or more plates extends over the interconnect in the interior region. A plate of the two or more plates is electrically coupled to a last metal wiring level of the interconnect.

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a back end of line (BEOL) wiring layer including metal lines and a first area between the metal lines. The integrated circuit structure also includes a metal-insulator-metal (MIM) capacitor formed in the first area. The MIM capacitor includes a first electrode, a first dielectric layer formed on the first electrode, a second electrode formed on the first dielectric layer, a second dielectric layer formed on the second electrode, a third electrode formed on the second dielectric layer, a third dielectric layer formed on the third electrode, a fourth electrode formed on the third dielectric layer, a first metal interconnect electrically connecting the first electrode and the third electrode, and a second metal interconnect electrically connecting the second electrode to the fourth electrode.

Abstract: Method and resistive structure is provided herein. The resistive structure includes a semiconductor substrate comprising one or more circuit elements and a first interconnect layer disposed on the substrate. The first interconnect layer is between a resistive layer and the semiconductor substrate. A dielectric layer is disposed between the first interconnect layer and the resistive layer. A via extending through the dielectric layer forms an electrical connection between the first interconnect layer and the resistive layer.

Abstract: Embodiments of the present invention are directed to methods and resulting structures for integrated circuits having metal-insulator-metal (MIM) capacitors that serve as both decoupling capacitors and crack stops. In a non-limiting embodiment, an interconnect is formed on a first portion of a substrate in an interior region of the integrated circuit. A second portion of the substrate is exposed in an edge region of the integrated circuit. A MIM capacitor is formed over the second portion of the substrate in the edge region. The MIM capacitor includes two or more plates and one or more dielectric layers. Each dielectric layer is positioned between an adjacent pair of the two or more plates and a portion of the two or more plates extends over the interconnect in the interior region. A plate of the two or more plates is electrically coupled to a last metal wiring level of the interconnect.

Abstract: A phase change memory (PCM) cell in an integrated circuit and a method of fabricating it involve depositing a layer of PCM material on a surface of a dielectric, and patterning the layer of PCM material into a plurality of PCM blocks. Heater material is formed on both sidewalls of each of the plurality of the PCM blocks to form a plurality of PCM cells. Each of the plurality of the PCM blocks and the heater material on both the sidewalls represents a PCM cell. An additional layer of the dielectric is deposited above and between the plurality of the PCM cells, and trenches are formed in the dielectric. Trenches are formed in contact with each side of each of the plurality of the PCM cells. Metal is deposited in each of the trenches. Current flow in the metal heats the heater material of one of the PCM cells.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes a substrate extending along a first direction to define a length, a second direction orthogonal to the first direction to define a width, and a third direction orthogonal to the first and second direction to define a height. The substrate includes a first capacitance region and a second capacitance region. The first capacitance region has a first maximum operating voltage (Vmax) and the second capacitance region has a second Vmax that is greater than the first Vmax.

Abstract: Embodiments of the present invention are directed to methods and resulting structures for integrated circuits having metal-insulator-metal (MIM) capacitors that serve as both decoupling capacitors and crack stops. In a non-limiting embodiment, an interconnect is formed on a first portion of a substrate in an interior region of the integrated circuit. A second portion of the substrate is exposed in an edge region of the integrated circuit. A MIM capacitor is formed over the second portion of the substrate in the edge region. The MIM capacitor includes two or more plates and one or more dielectric layers. Each dielectric layer is positioned between an adjacent pair of the two or more plates and a portion of the two or more plates extends over the interconnect in the interior region. A plate of the two or more plates is electrically coupled to a last metal wiring level of the interconnect.

Abstract: A resistive random access memory (RRAM) device and a method for constructing the device is described. A capping layer structure is provided over a bottom contact where the capping layer includes a recess situated over the bottom contact. A first portion of the recess is filled with a lower electrode such that the width of the recess defines the width of the lower electrode. A second portion of the recess is filled with a high-K layer so that a bottom surface of the high-K layer has a stepped profile. A top electrode is formed on the high-K layer and a top contact is formed on the top electrode. The width of the high-K layer is greater than the width of the lower electrode to prevent shorting between the top contact and the lower electrode of the RRAM device.

Abstract: A semiconductor including a short channel device including a vertical FET (Field-Effect Transistor), and a long channel device comprising a second vertical FET integrated with the short channel device. The long channel device including a plurality of short channel devices.

Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a back end of line (BEOL) wiring layer including metal lines and a first area between the metal lines. The integrated circuit structure also includes a metal-insulator-metal (MIM) capacitor formed in the first area. The MIM capacitor includes a first electrode, a first dielectric layer formed on the first electrode, a second electrode formed on the first dielectric layer, a second dielectric layer formed on the second electrode, a third electrode formed on the second dielectric layer, a third dielectric layer formed on the third electrode, a fourth electrode formed on the third dielectric layer, a first metal interconnect electrically connecting the first electrode and the third electrode, and a second metal interconnect electrically connecting the second electrode to the fourth electrode.

Abstract: Re-depositing of metal-containing particles of an embedded electrically conductive structure onto sidewalls of an overlying metal-containing structure is alleviated in the present application by providing a pedestal structure between the embedded electrically conductive structure and the metal-containing structure, wherein the pedestal structure has a flared sidewall that extends beyond a perimeter of the embedded electrically conductive structure. Such a pedestal structure (which can be referred to herein as a footing flare pedestal structure) mitigates, and in some embodiments, entirely eliminates, the exposure of the embedded electrically conductive structure during the patterning of metal-containing layers formed atop the embedded electrically conductive structure.

Abstract: A structure (interconnect or memory structure) is provided that includes a first electrically conductive structure having a concave upper surface embedded in a first interconnect dielectric material layer. A metal-containing cap having a convex bottom surface directly contacts the concave upper surface of the first electrically conductive structure. A metal-containing structure having a planar bottommost surface directly contacts a planar topmost surface of the metal-containing cap. A second electrically conductive structure contacts the planar topmost surface of the metal-containing structure. A second interconnect dielectric material layer is present on the first interconnect dielectric material layer and is located laterally adjacent to an upper portion of the metal-containing cap, the metal-containing structure, and the second electrically conductive structure.

Abstract: A switchable metal insulator metal capacitor (MIMcap) and a method for fabricating the MIMcap. In another aspect of the invention operating the MIMcap is also described. A first capacitor plate and a second capacitor plate are separated by a capacitor dielectric and disposed over a substrate. A first via is electrically connected to the first capacitor plate and comprised of phase change material (PCM). The PCM is deposited in an electrically conductive state and convertible by application of heat to an insulating state. A first heater is proximate to and electrically isolated from the PCM in the first via. When the first heater is activated it converts the PCM in the first via to the insulating state. This isolates the first capacitor plate from an integrated circuit.

Abstract: Metal e-fuse structure formed during back-end-of-line during processing and integral with on-chip metal-insulator-metal (MIM) capacitor (MIMcap). The metal e-fuse structures are extensions of MIMcap electrodes and are structured to isolate BEOL MIM capacitors for trimming and/or to isolate shorted or rendered highly leaky due to in process, or service induced defects. In one embodiment, the method incorporates the integral, co-processed metal e-fuse in series between the MIM capacitor and an active circuit. When a high current passes through the e-fuse element, the e-fuse element is rendered highly resistive or electrically open thereby disconnecting the MIM capacitor or electrode plate from the active circuitry. The e-fuse structure may comprise a thin neck portion(s) or zig-zag neck portion that extend from an MIMcap electrode away from the MIMcap between two inter-level interconnect via structures.

Abstract: A semiconductor and a method of forming a semiconductor on a single chip, including forming a shallow trench isolation (STI) region on a short channel device and a long channel device, forming at least two vertical fins connected in the long channel device, and forming contacts on a source and drain regions for the long channel device and short channel device, wherein the contacts connect a top surface of the source or drain region for series FET (Field-Effect Transistor) connection for the long channel device.