Abstract: Metal e-fuse structure formed during back-end-of-line during processing and integral with on-chip metal-insulator-metal (MIM) capacitor (MIMcap). The metal e-fuse structures are extensions of MIMcap electrodes and are structured to isolate BEOL MIM capacitors for trimming and/or to isolate shorted or rendered highly leaky due to in process, or service induced defects. In one embodiment, the method incorporates the integral, co-processed metal e-fuse in series between the MIM capacitor and an active circuit. When a high current passes through the e-fuse element, the e-fuse element is rendered highly resistive or electrically open thereby disconnecting the MIM capacitor or electrode plate from the active circuitry. The e-fuse structure may comprise a thin neck portion(s) or zig-zag neck portion that extend from an MIMcap electrode away from the MIMcap between two inter-level interconnect via structures.

Abstract: A dielectric spacer is formed laterally adjacent to a bottom conductive structure. The dielectric spacer is configured to limit the area in which a subsequently formed top contact structure can contact the bottom conductive structure. In some embodiments, only a topmost surface of the bottom conductive structure is contacted by the top contact structure. In other embodiments, a topmost surface and an upper sidewall surface of the bottom conductive structure is contacted by the top contact structure.

Abstract: Interconnect structures or memory structures are provided in the BEOL in which topography variation is reduced. Reduced topography variation is achieved by providing a structure that includes a first dielectric capping layer that has a planar topmost surface and/or a second dielectric capping layer that has a planar topmost surface. The first dielectric capping layer has a non-planar bottom surface that contacts both a recessed surface of an interconnect dielectric material layer and a planar topmost surface of at least one electrically conductive structure that is embedded in the interconnect dielectric material layer.

Abstract: An anti-fuse device having enhanced programming efficiency is provided. The anti-fuse device includes via contact structures that have different critical dimensions located between a first electrode and a second electrode. Notably, a first via contact structure having a first critical dimension is provided between a pair of second via contact structures having a second critical dimension that is greater than the first critical dimension. When a voltage is applied to the device, dielectric breakdown will occur first through the first via contact structure having the first critical dimension.

Abstract: An eFuse structure including a semiconductor substrate; back end of the line (BEOL) metallization levels on the semiconductor substrate; vias extending through the metallization levels; at least one of the metallization levels including one or more metallic plates in electrical contact with one of the vias, the one or more metallic plates having at least one fusible link in electrical contact with one or more additional vias. The eFuse structure may form a multi-fuse structure such that each fusible link may be fused separately or together at the same time.

Abstract: Re-depositing of metal-containing particles of an embedded electrically conductive structure onto sidewalls of an overlying metal-containing structure is alleviated in the present application by providing a pedestal structure between the embedded electrically conductive structure and the metal-containing structure, wherein the pedestal structure has a flared sidewall that extends beyond a perimeter of the embedded electrically conductive structure. Such a pedestal structure (which can be referred to herein as a footing flare pedestal structure) mitigates, and in some embodiments, entirely eliminates, the exposure of the embedded electrically conductive structure during the patterning of metal-containing layers formed atop the embedded electrically conductive structure.

Abstract: A method of increasing the surface area of a contact to an electrical device that in one embodiment includes forming a contact stud extending through an intralevel dielectric layer to a component of the electrical device, and selectively forming a contact region on the contact stud. The selectively formed contact region has an exterior surface defined by a curvature and has a surface area that is greater than a surface area of the contact stud. An interlevel dielectric layer is formed on the intralevel dielectric layer, wherein an interlevel contact extends through the interlevel dielectric layer into direct contact with the selectively formed contact region.

Abstract: Embodiments are directed to a method and resulting structures for forming low resistance, high capacitance density MIM capacitors. In a non-limiting embodiment, one or more bottom plate contacts are formed over a substrate. A bottom capacitor plate is formed directly on a top surface and a sidewall of each of the one or more bottom plate contacts. A capacitor dielectric layer is formed directly on a surface of the bottom capacitor plate. A top capacitor plate is formed directly on a surface of the capacitor dielectric layer. A first portion of the top capacitor plate extends past a sidewall of the bottom capacitor plate in a direction parallel to the substrate. A top plate contact is formed directly on the first portion of the top capacitor plate.

Abstract: An IC device includes an integrated capacitor and anti-fuse. Prior to programming of the anti-fuse, electrical current is configured to flow siloed between a first circuit element and a second circuit element through a first VIA. The anti-fuse may be programed by applying a fusing voltage to a second VIA to charge an anti-fuse plate. Within the anti-fuse, the anti-fuse plate is separated from the first capacitor plate by a dielectric. The fusing voltage causes an electric field between the plates to exceed a breakdown field strength of the dielectric which results in an electric arc between the anti-fuse plate and the capacitor plate. The electric arc fuses or otherwise joins the anti-fuse plate and the capacitor plate. Functionality of the IC device may be altered by allowing or driving current from the first circuit element or the second circuit element across the fused plates.

Abstract: An IC device includes a simultaneously formed capacitor and resistor structure. The capacitor and resistor may be located between a Back End of the Line (BEOL) interconnect stack and an external device interconnect pad of the IC device. The resistor may be used to step down a voltage applied across the resistor. The resistor may include one or more resistor plates that are formed simultaneously with a respective one or more plates of the capacitor. For example, a capacitor plate and a resistor plate may be patterned and formed from the same conductive sheet. Each of the resistor plates may be connected to one or more vertical interconnect accesses (VIA).

Abstract: An IC device, such as a wafer, chip, die, processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), or the like include a chamfered VIA that connects an upper wiring line and a first lower wiring line. The chamfered VIA includes a chamfer or fillet upon the edge that connects the VIA sidewall(s) with the VIA contact surface that is connected to the first lower wiring line. The chamfer or fillet effectively increases the amount of a dielectric material, such as a high-k dielectric material, within a trench of the VIA and that is between the chamfered VIA and a second lower wiring line that neighbors the first lower wiring line. This increased dielectric material improves TDDB between the chamfered VIA and the second lower wiring line and mitigates TDDB effects, such as electrical shorts between the chamfered VIA and the second lower wiring line.

Abstract: An electrode structure is located at least partially in a via opening having a small feature size and containing a fuse element which is composed of a fuse element-containing seed layer that is subjected to a reflow anneal. The electrode structure is composed of a material having a higher electromigration (EM) resistance than the material that provides the fuse element. Prior to programming, the fuse element is present along sidewalls and a bottom wall of the electrode structure. After programming, a void is formed in the fuse element along at least one sidewall of the electrode structure and the resistance of the device will increase sharply.

Abstract: An interconnect level is provided on a surface of a substrate that has improved crack stop capability. The interconnect level includes at least one wiring region including an electrically conductive structure embedded in an interconnect dielectric material having a dielectric constant of less than 4.0, and a crack stop region laterally surrounding the wiring region. The crack stop region includes a crack stop dielectric material having a dielectric constant greater than the dielectric constant of the interconnect dielectric material. The crack stop region may be devoid of any metallic structure, or it may contain a metallic structure. The metallic structure in the crack stop region, which is embedded in the crack stop dielectric material, may be composed of a same, or different, electrically conductive metal or metal alloy as the electrically conductive structure embedded in the interconnect dielectric material.

Abstract: A method for constructing an advanced crack stop structure is described. An interconnection structure is formed comprised of a plurality of levels. Each level has an interconnect structure section and a crack stop section. In a first level of the interconnection structure, a high modulus layer is formed in the crack stop recess but not the interconnect recess and a barrier layer and a conductive metal layer is formed in both the interconnection recess and the crack stop recess of the first level. In a second level of the interconnection structure and the crack stop structure, a second high modulus layer is formed in the crack stop recess but not the interconnect recess and a barrier layer and a conductive metal layer is formed in both the interconnection recess and the crack stop recess of the second level. The barrier layers and high modulus layers are deposited in different steps.

Abstract: An interconnect or memory structure is provided that includes a first electrically conductive structure having a concave upper surface embedded in a first interconnect dielectric material layer. A first metal-containing cap contacts the concave upper surface of the first electrically conductive structure. The first metal-containing cap has a topmost surface that is coplanar with a topmost surface of the first interconnect dielectric material layer. A second metal-containing cap having a planar bottommost surface contacts the topmost surface of the first metal-containing cap. A metal-containing structure having a planar bottommost surface contacts a planar topmost surface of the second metal-containing cap.

Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.

Abstract: An interconnect structure is provided that includes a liner located between an electrically conductive structure and an interconnect dielectric material layer. The liner is composed of a phase change material that is insulating at a first temperature, and becomes conductive at a second temperature that is higher than the first temperature. The liner that is composed of such a phase change material is referred to as an “insulator-to/from metal transition (IMT)” liner. In the present application, an entirety of, or a portion of, the IMT liner may be changed from an insulating phase to a conductive phase by increasing the temperature (i.e., heating) of the liner so as to provide a redundancy path in which electrons can flow.

Abstract: According to an embodiment of the present invention, a method for forming contacts includes forming an oxide layer over and along a first liner layer. A first spacer layer is formed along the first liner layer opposing the oxide layer. A work function metal layer is formed along the first spacer layer opposing the first liner layer. A gate is formed on and along the work function metal opposing the first spacer. A second spacer layer is formed on the oxide layer. Portions of the oxide layer, the first liner layer, the first spacer, the work function metal layer and the second spacer layer are removed which forms a recess between the gate and the first spacer layer. A second liner layer is deposited in the recess. A low-resistance metal is deposited in the removed portions to form the first contact.

Abstract: A switchable metal insulator metal capacitor (MIMcap) and a method for fabricating the MIMcap. In another aspect of the invention operating the MIMcap is also described. A first capacitor plate and a second capacitor plate are separated by a capacitor dielectric and disposed over a substrate. A first via is electrically connected to the first capacitor plate and comprised of phase change material (PCM). The PCM is deposited in an electrically conductive state and convertible by application of heat to an insulating state. A first heater is proximate to and electrically isolated from the PCM in the first via. When the first heater is activated it converts the PCM in the first via to the insulating state. This isolates the first capacitor plate from an integrated circuit.

Abstract: A structure (interconnect or memory structure) is provided that includes a first electrically conductive structure having a concave upper surface embedded in a first interconnect dielectric material layer. A metal-containing cap having a convex bottom surface directly contacts the concave upper surface of the first electrically conductive structure. A metal-containing structure having a planar bottommost surface directly contacts a planar topmost surface of the metal-containing cap. A second electrically conductive structure contacts the planar topmost surface of the metal-containing structure. A second interconnect dielectric material layer is present on the first interconnect dielectric material layer and is located laterally adjacent to an upper portion of the metal-containing cap, the metal-containing structure, and the second electrically conductive structure.