Abstract: A capacitive touch-sensitive panel, including a plurality of sense electrodes biased at a fixed voltage relative to a common guard electrode, and a measuring circuit comprising: a power management integrated circuit comprising a voltage source generating a modulation voltage that is available at a guard terminal of the power management integrated circuit that is in electric connection with the guard electrode, one or more slave integrated circuits, each connected to a plurality of sense electrodes and comprising a Capacity-to-Digital converter or a plurality of Capacity-to-Digital converters that are operatively arranged for generating digital measure codes representing the instantaneous electric capacity of sense electrodes; floating communication means allowing transfer of command, timing signals and/or measure codes between the master integrated circuit and said slave integrated circuits.

Abstract: A current and/or voltage band gap reference circuit includes a current mirror circuit having first, second and third current outputs, a first resistive element, and first and second nanotube transistors. The nanotube diameter of the first transistor is different to the nanotube diameter of the second transistor, allowing variable band-gaps to be achieved. A method for designing the circuit includes selection of the nanotube diameters.

Abstract: A photodetector (105) generates an electrical signal that has a value that changes approximately linearly at a rate that is proportional to an amount of light intensity incident on a photodetector since a most recent reset command was received at a reset input of the photodetector. A measurement circuit (110) generates a comparison state that is based on a comparison of the value of the photodetector signal to a reference signal in response to one of a plurality a sample pulses. A control circuit (160) generates the plurality of sample pulses at non-uniform time intervals and generates an elapsed time as an accumulation of the non-uniform time intervals occurring from the reset command to a change of the comparison state. In one embodiment, the reciprocal of an accumulated duration of the non-uniform time intervals is a linear function of a number of time intervals after the reset command.

Abstract: An anti-blooming charge accumulation pixel using an anti-blooming element coupled to the pixel prevents blooming by ensuring that a voltage of a charge accumulation device of the pixel is always returned to a clamping voltage following comparison events. The anti-blooming element is used to return the voltage across a photodiode to the supply voltage when both a low voltage comparison and a high voltage comparison have occurred. A control block is used to determine an input signal to the anti-blooming element based upon the result of a low voltage comparison and a high voltage comparison. The input signal can be used to drive the anti-blooming element to a desired logic level, thereby causing the voltage across the charge accumulation device to be the clamping voltage. The use of the anti-blooming element eliminates blooming to adjacent pixels, independent of an integration time of the pixel.

Abstract: A photodetector (105) generates an electrical signal that has a value that changes approximately linearly at a rate that is proportional to an amount of light intensity incident on a photodetector since a most recent reset command was received at a reset input of the photodetector. A measurement circuit (110) generates a comparison state that is based on a comparison of the value of the photodetector signal to a reference signal in response to one of a plurality a sample pulses. A control circuit (160) generates the plurality of sample pulses at non-uniform time intervals and generates an elapsed time as an accumulation of the non-uniform time intervals occurring from the reset command to a change of the comparison state. In one embodiment, the reciprocal of an accumulated duration of the non-uniform time intervals is a linear function of a number of time intervals after the reset command.

Abstract: An anti-blooming charge accumulation pixel using an anti-blooming element coupled to the pixel prevents blooming by ensuring that a voltage of a charge accumulation device of the pixel is always returned to a clamping voltage following comparison events. The anti-blooming element is used to return the voltage across a photodiode to the supply voltage when both a low voltage comparison and a high voltage comparison have occurred. A control block is used to determine an input signal to the anti-blooming element based upon the result of a low voltage comparison and a high voltage comparison. The input signal can be used to drive the anti-blooming element to a desired logic level, thereby causing the voltage across the charge accumulation device to be the clamping voltage. The use of the anti-blooming element eliminates blooming to adjacent pixels, independent of an integration time of the pixel.

Abstract: Composite semiconductor structures and devices are presented in which digital processing systems are formed. The structures and devices include a first semiconductor material (which can be a Group IV semiconductor such as silicon), an accommodating layer (which can be an oxide or nitride), and a second semiconductor material (which can be a compound semiconductor such as gallium arsenide). The first and second semiconductor materials and accommodating layer can be fabricated as a single integrated circuit chip. Computationally intensive functions, such as arithmetic logic functions, and other digital processing functions requiring high speed operation, such as information transfer, can be formed in the second semiconductor material while other functions, such as control and memory, can be formed in the first semiconductor material. Such formation of digital processing systems improves system performance.

Abstract: Integrated communications apparatus and methods are used to receive, transmit, and operate on communications signals. A composite semiconductor structure may be formed for providing an integrated communications device that may include transceiver circuitry, data converter circuitry, and processor circuitry. The data converter circuitry may include an analog-to-digital and/or digital-to-analog data converter that is implemented at least partly using compound semiconductors (e.g., using compound semiconductor transistors for implementing comparators and/or switches in the data converter). The processor circuitry may include some circuitry that is formed from non-compound semiconductors, which is better suited than compound semiconductors to perform digital signal processing operations. The transceiver circuitry may include compound and/or non-compound semiconductor circuitry depending on the signal frequency and whether the signal is optical or electrical.

Abstract: A monolithic, software-definable, power amplifier is provided. According to one embodiment of the invention, power amplifier circuits can be tuned to the most efficient power amplification characteristics as determined by a digital microprocessor based on varying data. The data may relate to user density, carrier frequency and spectral band. The power amplifier circuits may also be formed on semiconductor structures that include monocrystalline silicon substrates and layers of monocrystalline compound semiconductors. In these structures, the power amplifier may be integrated in a single integrated circuit wherein portions of the power amplifier circuits may be formed on the silicon substrate and portions may be formed on the compound semiconductor. This configuration may substantially increase efficiency of the integrated power amplifier according to the invention.

Abstract: A composite integrated circuit with electrical isolation is provided. The composite integrated circuit includes a Group IV semiconductor portion and a compound semiconductor portion. The composite integrated circuit includes electrical signal processing circuitry that is formed at least partly from the Group IV semiconductor portion. The composite integrated circuit includes circuitry that allows the processing circuitry to communicate via an electrical connection with the external circuitry and an optical connection that is provided by a pair of optical components that are at least partly formed in the compound semiconductor portion. The optical connection electrically insulates the processing circuitry from electrical signals in the electrical connection.

Abstract: A portable 2-way secure financial messaging unit (906) includes a receiver (804), a selective call decoder (1004), a financial transaction processor (1014), a main processor (1006), and a transmitter (1034). A received secure financial transaction message is decoded by the selective call decoder (1004) and either passed directly to a financial transaction processor (1014) in the secure financial messaging unit or to a smart card to prevent unauthorized access to information contained in the secure financial transaction message. The portable 2-way secure financial messaging unit (906) may originate as well as receive financial transactions.

Abstract: A selective call receiver (500) includes a radio receiver (501) and a processor (508). The radio receiver includes an antenna (502), a combination circuit (204), a bandpass filter (208), mixers (212, 214), analog-to-digital converters (222, 224), digital mixers (234, 236), a second combination circuit (242), and a digital-to-analog converter (246). The combination circuit receives an analog signal from the antenna and combines the same with an analog feedback signal generated by the digital-to-analog converter. The bandpass filter filters the output of the combination circuit and supplies its output to the mixers which down-convert the signal to baseband signals. These signals are modified by the analog-to-digital converters to digital signals which are up-converted by the digital mixers. The outputs of the digital mixers are combined by the second combination circuit to a digital output that is modified by the digital-to-analog converter to the analog feedback signal.

Abstract: A random number generator includes a sample clock having a sample clock rate, a chaotic oscillator having a characteristic upper frequency, and an output section. The chaotic oscillator includes a quantized linear section and a non-linear section. The quantized linear section includes multiple quantized integrators coupled to the sample clock and intercoupled in a linear intercoupling. The non-linear section is coupled in a feedback manner with the quantized linear section. The output section generates a random binary output signal having the sample clock rate, formed by a logical combination of binary signals, of which one binary signal is generated by each of the multiple quantized integrators. Each quantized integrator includes an analog to digital converter that preferably includes a sigma delta converter that generates one of the binary signals.

Abstract: A first complementary metal oxide semiconductor (CMOS) current reference circuit (100, 500) has a first and a second current mirror (110, 150) and is implemented using one of bulk wafer technology and silicon on insulator (SOI) technology. The first current mirror (110) has an output stage (130) that includes at least one cascode coupled field effect transistor (FET) (125) having one of a source tied well (when implemented using bulk wafer technology) or a source tied body (when implemented using SOI technology). A second CMOS current reference circuit (600, 800) has a first and a second current mirror (650, 610) and is implemented using SOI technology. The first current mirror (650) has a first bias FET (161) having a gate tied body.

Abstract: A low input prescaler (800) that is responsive to input signals having low amplitude alternating current (AC) components includes a switched tunable prescaler (280) that generates a prescaler output signal (221) having a prescaler output frequency during an operational state of the prescaler and having a free-running frequency that is responsive to a tuning control signal (216) during a tuning state of the prescaler. A frequency comparator (235) generates a comparator output in response to a difference between a reference frequency and the prescaler output frequency. A prescaler tuner (290, 390) adjusts the tuning control signal in response to the comparator output during the tuning state to minimize the difference between the reference frequency and the prescaler output frequency, and holds the tuning control signal during the operational state. The prescaler is used in phase lock loops (200, 400, 600) and other circuits.

Abstract: A voltage splitter circuit (100) that generates a one-half supply voltage includes a first switched operational transconductance amplifier (switched OTA) (120), a first transistor switch (110) that is controlled by a first clock signal (108) to periodically switch a first supply voltage (135) to a non-inverting input (118) of the first switched OTA, a second switched OTA (115), a second transistor switch (105) that is controlled by an inverted second clock signal (104) to periodically switch a second supply voltage (130) to a non-inverting input (114) of the second switched OTA, a commutating capacitor (112) coupled between the non-inverting input of the first switched OTA and the non-inverting input of the second switched OTA, a first filter capacitor (145) coupled to an output (121) of the first switched OTA, a second filter capacitor (140) coupled to an output (116) of the second switched OTA, and a third switched OTA (125). The first and second clock signals are non-overlapping.

Abstract: A method is used by a detector (102) for extending the operating frequency range of a phase lock loop (100). The detector (102) detects a phase-frequency difference between a reference signal (109) and a generated signal (108) of the phase lock loop (100). The detector (102) includes a divider (202) for counting transitions of the generated signal (108) and a logic element (204) and counter (212) for detecting when the frequency of the generated signal (108) is such that the divider (202) operates outside its linear frequency range in relation to a predetermined transition of the reference signal (109). The detector (102) further includes a register (206) for recording a phase value of the divider (202) coincident with the predetermined transition, or a constant phase value (304, 306) when the frequency of the generated signal (108) is operating outside of the linear range of the divider (202).

Abstract: A resistorless amplifier circuit uses integrated operational transconductance amplifiers to realize a plurality of circuit transfer functions. The preferred embodiment produces an output signal voltage V.sub.out (500) that is either g.sub.m1 /g.sub.m3 or g.sub.m1 /(g.sub.m3 -g.sub.m1) times the input signal voltage V.sub.in (400). Additionally, an alternative embodiment implements a resistorless summing and subtracting operational transconductance amplifier circuit that realizes an output signal voltage as follows: ##EQU1## The resistorless amplifier circuit includes a first operational transconductance amplifier (100) with a transconductance g.sub.m1, a second operational transconductance amplifier (200) with a transconductance g.sub.m2, and a third operational transconductance amplifier (300) with a transconductance g.sub.m3.

Abstract: A phase lock loop of a synthesizer (143) is controlled by applying (506) modern optimal control techniques for a predetermined period in a computing engine (222), in response to an error being introduced into a signal of the phase lock loop, and by utilizing (510) classical control techniques for controlling the phase lock loop after the predetermined period.

Abstract: A communication receiver (100) utilizing a synthesizer (143) employs a discrete-time phase locked loop which includes a reference oscillator (135), a phase error detector (202), a discrete-time analog computing element (206), an integrator (210), a controlled frequency generator (211, 212), and a frequency divider (214). The discrete-time analog computing element implements a discrete-time analog lead-lag network circuit. This circuit includes a clock and logic circuit (216), at least one discrete-time analog queuing element (218), and an analog computing engine (222). The queuing element (218) includes N analog signal lines, N analog storage lines, N control lines, and N.sup.2 controllable switches. Each controllable switch is coupled between each of the N analog signal lines and each of the N analog storage lines. In addition, N charge storage elements are coupled between each of the N analog storage lines and a common circuit node.