Abstract: A differential voltage comparator circuit comprises a differential pair (802 and 804) electrically coupled to a biasing network (806) and a loading network (808). The differential pair circuit comprises a first (802) and a second (804) controllable electron valves arranged in a differential pair configuration. The first and second electron valve drains (811 and 810) are electrically coupled to the loading network (808). The first and second electron valve sources (822 and 824) are electrically coupled to the biasing network (806). The first and second electron valve control gates (834 and 836) are electrically coupled to respective first and second input voltage potentials (V1 and V2). Lastly, the first and second electron valve bodies (812 and 814) are electrically coupled to respective first and second body effect voltage potentials (VB1 and VB2) that are not the same voltage potential.

Abstract: A circuit (200) for generating a first (EL1) and second (EL2) drive signals and limiting a maximum voltage of each of the drive signals (EL1, EL2). The circuit (200) further samples the drive signals (EL1, EL2) to provide a voltage source (Vdd).

Abstract: A reconfigurable deinterleaver for deinterleaving up to N interleaved codewords, each up to M bits in length comprises a memory array, a memory for storing predetermined deinterleaver parameters, a controller, and column and row selector means. The memory array is configured with N bit rows by M bit columns, and is capable of selectably deinterleaving interleaved codewords. The predetermined deinterleaver parameters define the number and length of the interleaved codewords to be deinterleaved. The controller is responsive to the deinterleaver parameters for controlling the writing of interleaved codewords into the memory array and for reading deinterleaved codewords from the memory array. Column and row selector means provide for writing interleaved codewords into, and reading deinterleaved codewords from only a portion of the memory array when smaller data blocks are deinterleaved.

Abstract: A paging receiver has a synthesizer for governing the receive frequency. The paging receiving further has characteristics which are varied in response to the receive frequency. These characteristics include varying the bandwidth of a loop filter within a phase lock loop within the synthesizer as well as varying the time in which a detector circuit used to extract a DC level from a recovered audio signal is disabled. Furthermore, the bandwidth of the loop filter is varied in response to switching from a first receive frequency to a second receive frequency in order to provide for either a uniform frequency lock time or for a rapid frequency lock time. Furthermore, the time in which the detector circuit is disabled is correspondingly changed.

Abstract: A voltage multiplier selectively couples an input voltage potential (10) from a voltage source (Vin) to an energy storage device (22) in response to a first control circuit (18). A second switching circuit (26) is used to selectively serially couple the first energy storage device (22) and the voltage source (10) to provide an intermediate voltage potential (Vin), which is selectively coupled to a second energy storage device (30) in response to a second control signal (28') that is provided by a second control circuit (38) coupled to the intermediate voltage potential (Vim). The output of the second energy storage device (30) comprises an output voltage potential (Vout) being greater than the input voltage potential (Vin).

Abstract: An apparatus is described for the dual modulus prescaling of a high frequency signal. The apparatus comprises a dual modulus divider, second divider, synchronization circuit for providing a first modulus control signal to the dual modulus divider, and means for coupling the output of the second divider to the input of the synchronization circuit when a second modulus control signal is in a first state.

Abstract: A high speed CMOS divide by 4/5 prescaler circuit comprises first, second, third, fourth, and fifth inverter stages. When a modulas control signal is low, the prescaler operates as five clocked inverters in series having an output which is fed back to the input of the initial stage. That is, the circuit operates as a five stage clocked ring oscillator wherein only one output changes on each clock edge. When a modulas control signal is high indicating that a divide by four is desired, the counter operates as a five stage ring oscillator for seven clock edges. On the eighth edge, feed forward circuitry forces the last three stages to change states simultaneously.

Abstract: A method of and apparatus for automatically selecting one of first and second loop bandwidth states of a phase lock loop circuit of a frequency synthesizer. The phase lock loop circuit is governed by a reference frequency signal and a feedback frequency signal to adjust the frequency of the synthesized frequency signal to a frequency channel setting. Each of the reference and feedback frequency signals include one phase indication per frequency period. The feedback frequency signal is phase and frequency representative of the synthesized frequency signal.

Abstract: A frequency synthesizer which has at least one programmably characterized phase lock loop circuit includes a buffer memory and an interface controller responsive to operational codes received from a central controller to direct transfer of data words for characterization of the phase lock loop circuit among the at least one phase lock loop circuit, the buffer memory, and the central controller. In one embodiment, the transfer of data words between the central controller and phase lock loop circuit or buffer memory are performed serially in accordance with a prespecified protocol and governed by a clock signal generated by the central controller. Data word transfers between the buffer memory and at least one phase lock loop circuit may also be performed serially in accordance with a prespecified protocol, but may be governed autonomously by an internal clock signal generated by the frequency synthesizer.

Abstract: A frequency synthesizer which includes at least one phase lock loop operative in a selected loop bandwidth state includes a dynamically programmable control circuit for setting the frequency range of its selected loop bandwidth state. In another aspect, the frequency synthesizer may include a plurality of phase lock loop circuits; and a common bias circuit programmably operative to generate at least one bias signal which is coupled commonly to the plurality of phase lock loop circuits for setting a common frequency range for the loop bandwidth states of all of the phase lock loop circuits.

Abstract: A dual bandwidth crystal controlled oscillator is described having a first transconductance amplifier providing sufficient gain to maintain oscillation with an oscillator crystal at a minimum current drain. A second transconductance amplifier is provided which can be selectively coupled to the first transconductance amplifier, thereby augmenting the gain of the first transconductance amplifier to provide the capability for rapid oscillator start-up following battery saver operation. The dual bandwidth crystal controlled oscillator can be utilized in conventional oscillator and frequency synthesizer applications.

Abstract: A microcomputer having predetermined clock pulse frequency requirements receives pulses from a multiplying type frequency synthesizer which utilizes a reference frequency less than the largest of the predetermined requirements. The synthesizer is responsive to program instructions to generate clock pulse frequencies sufficient to satisfy the requirement for immediate execution of programmed tasks. As the requirements change, the synthesizer responds to provide only the frequency required. Thus, the power dissipated by the microcomputer system is minimized.

Abstract: A frequency synthesizer governed by a battery saving signal having sleep and awake cycles comprises a phase locked loop and a control circuit for enhancing the restart operation of the phase locked loop at the commencement of each awake cycle of the battery saving signal. More specifically, the phase locked loop includes a phase detector for locking the frequencies generated by a reference oscillator and a voltage controlled oscillator by adjusting a signal in a storage device used for governing the voltage controlled oscillator. During the sleep and awake cycles of the battery saving signal, the oscillators and phase detector are inhibited and enabled, respectively, in their operations. In addition, the storage device maintains a desired governing signal for the voltage controlled oscillator during the sleep cycles. A problem arises as a result of the oscillators not being simultaneously effectively enabled at the commencement of an awake cycle.

Abstract: In system capable of self turn-off, a circuit arrangement for providing a controlled turn-off includes a detecting circuit for detecting actuation of a turn-off switch, thereby providing a turn-off authorization signal. A turn-off protection circuit is coupled to the detecting circuit and a controller is coupled to the turn-off protect circuit and the detecting circuit. The controller disables the turn-off protect circuit when the turn-off authorization is received and present. The controller generates a turn-off signal for powering the system down after the turn-off protect circuit has been disabled.

Abstract: An MOS crystal controlled oscillator circuit is provided which includes a pair of MOS transistors coupled together in complementary fashion to form a first non-inverting stage. The output of the first non-inverting stage is coupled to the input of a second non-inverting stage including a MOS transistor exhibiting a source follower configuration or a bipolar transistor exhibiting an emitter follower configuration. The output of the second non-inverting source follower stage is coupled via a feedback element, for example, a piezoelectric crystal, to the input of the first non-inverting stage. A feedback loop is thus formed which causes the circuit to resonate at a frequency determined by the piezoelectric crystal feedback device. This oscillator configuration results in a degree of insensitivity to variations in parasitic impedance of the piezoelectric crystal feedback device.

Abstract: In a resistance comparator circuit a current mirror provides a reference current to a first conduction path and a mirror current to a second conduction path. A first transistor is coupled in series with the first conduction path and a reference resistance is coupled in series with the first transistor. A second transistor is coupled in series with the second conduction path and an input resistor is placed in series with the second transistors. A bias circuit supplies a bias signal to the control nodes of the first and second transistor. A logic transition occurs when the input resistor is equal to the reference resistor or a predetermined multiple thereof.

Abstract: A high speed logic latching circuit consists of a pair of inverters and feedback switches used to latch the inverters. A pair of input switching means allows data to enter the latch when the latch is disabled. This configuration allows for high speed, reduced substrate area and true complementary outputs.