Abstract: A hybrid analog-digital phase error detector (107) is utilized for detecting a phase error between first and second clock signals (132, 104). Digital and analog phase error detectors (108, 116) are connected to the first and second clock signals (132, 104), and are utilized for producing digital and analog phase error values (110, 118). The digital and analog controllers (112, 120) connected to the digital and analog phase error detectors (108, 116) execute digital and analog control algorithms based on the digital and analog phase error values (110, 118) to produce digital and analog control signals (114, 122). A summer (124) connected to the outputs of the digital and analog controllers (112, 120) combines the analog control signal (122) and the digital control signal (114) to produce a composite control signal (126) representing the phase error.

Abstract: A method for full duplex communication between master and slave devices (403, 422) coupled by a serial peripheral interface (420) includes the steps of the slave device (422) updating a status register (421) based upon an event, after which the slave device (422) transmits a communication request to the master device (403). When the master device (403) thereafter takes the slave-select line low to initiate communication, the slave device (422) automatically transmits the contents of the status register (421) over the master-in-slave-out line. At the same time, the master device (403) transmits an "empty" byte of information over the master-out-slave-in line.

Abstract: A frequency synthesizer (100) is used for generating a plurality of signals operating at a plurality of frequencies that are integer multiples of a reference frequency. The frequency synthesizer (100) includes a plurality of phase lock loops coupled to a single phase error detector. The phase error detector (103) is connected to a reference signal (104), a first generated signal (116) and a sampler signal (136) derived from a second generated signal (132). The phase error detector (103) includes a shared counter (118), and first and second registers (106, 122) connected to the output of the shared counter (118). First and second phase lock loops (101, 105) are used for phase locking to the reference signal (104). The first and second phase lock loops (101, 105) derive phase error signals from the first and second registers (106, 122), thereby adjusting the first and second generated signals (116, 132).

Abstract: A communication receiver (100) employs a discrete time digital phase locked loop (142) for maintaining a generated signal (144) locked to a reference signal (136). The discrete time digital phase locked loop (142) includes a phase detector (202), an accumulator (219), an adder (227), and a controlled oscillator (232). The accumulator (219) is connected to the phase detector (202) and a reference signal (136) for calculating an accumulator output value equal to a first sum of a current sample generated by the phase detector (202), and all of the plurality of discrete phase error samples produced prior to the current sample. The adder (227) is connected to the phase detector (202) and the accumulator (219) for forming a second sum of the current sample and the accumulator output value. The controlled oscillator (232) receives the second sum, which is utilized for controlling the controlled oscillator (232).

Abstract: A method and apparatus determine an instantaneous phase difference (207) between a reference signal (103) and a controlled signal (120). The reference signal (103) is derived by frequency dividing a first signal by a counter (106) including an output (107) having K sequential states, wherein K is an integer value equal to the frequency of the first signal (103) divided by the frequency of the desired reference signal, and wherein the output (107) changes by no more than one bit between any adjacent states of the K sequential states. The output (107) of the counter (106) is recorded (206) at a time concurrent with a first predetermined event occurring in the controlled signal (120), thereby generating a recorded count value that is free from metastability induced errors. The recorded count value is decoded (208) to produce a sequential state number S.sub.E corresponding to the first predetermined event. The instantaneous phase difference (207) is then calculated (210) from S.sub.

Abstract: A method and apparatus for minimizing mean calculation rate in a processing system (510) performing active addressing calculations on a frame of data for driving a display (100) having a plurality of electrodes (104, 106) comprise a monitor (700) for monitoring (1506) pixel values in the frame of data to be processed and displayed. A comparator (720) compares (1508) adjacent monitored pixel values to determine (1510) resolution of the data, and thereafter a controller (622) controls (1610, 1612, 1614) the processing system (510) to minimize the mean calculation rate by modifying the active addressing calculations in accordance with the resolution determined.

Abstract: A detector circuit (301) is utilized in a DC to DC converter (300) having an inductor (356) coupled to a switch (358) for interrupting an electric current through the inductor (356), thereby allowing the inductor (356) to transfer stored energy to a capacitive load (364). The detector circuit (301) includes a capacitor (302) coupled to the inductor (356) for generating a transient current (428) in response to a completion of a transfer of stored energy from the inductor (356). The detector circuit (301) further includes a reference current generator (306) for generating a reference current, and a summing node (304) coupled to the capacitor (302) and coupled to the reference current generator (306) for summing the transient current (428) and the reference current. The two summed currents form a transient control current (436) responsive to the completion (424) of the transfer of stored energy from the inductor (356).

Abstract: A selective call receiver (100) includes a phase lock loop frequency synthesizer having a programmable output frequency signal (414) responsive to a control current signal (417). The phase lock loop frequency synthesizer includes a programmable gain current multiplier (412), a gain of which is determined by a control word selected such that a loop gain of the synthesizer remains relatively constant over a predetermined operating domain of a programmable output frequency signal (417). The current multiplier generates (412) the control current signal (417) by subtracting a reference current (415) from a limited current (416), thus bounding a range of the control current signal (417) within a maximum value of substantially the reference current (415) and a minimum value of the difference between the reference current (415) and the limited current (416).

Abstract: A cascode amplifier circuit including an input mirroring transistor (401) that generates a first output current (403) in response to the input signal. A diode connected transistor (404) generates a control bias proportional to the first output current. A cascode connected transistor output stage (405) includes a common source transistor (406) coupled to the input signal and the input mirroring transistor (401) for establishing an output current (407) in the cascode connected transistor output stage. A common gate transistor (408) is coupled to the diode connected transistor (404) and the common source transistor (406) for isolating the common source transistor (406) from any change in an output voltage present at an output terminal (409) of the common gate transistor (408) while operating to control the output currently(407) in response to the control bias.

Abstract: A complementary cascode push-pull amplifier circuit includes a bias generator, a complementary bias generator, a cascode input stage (416, 417), a cascode output stage (410, 411), a complementary cascode input stage (456,457), and a complementary cascode output stage (450,451). The bias generator is responsive to a first input signal (420) and generates a bias control voltage. The complementary bias generator is responsive to a second input (421) and generates a complementary bias control voltage. The cascode output stage (410, 411) and the complementary cascode output stage (450,451) each have an output coupled to a common output terminal (510) for generating a portion of an output current signal in response to the respective input signals (420, 421) and in response to the bias control voltage and the complementary bias control voltage being generated.

Abstract: A multi-output integrated circuit amplifier (500) consists of a first primary current mirror (510), and a plurality of secondary current mirrors (520). The first primary current mirror (510) implemented in a single substrate and having a first primary input (511). The first primary current mirror (510) generates a plurality of first inverted primary current outputs in response to a first current signal coupled to the first primary input (511). The plurality of secondary current mirrors are implemented in the same single substrate and each has a secondary input coupled to a unique one of the plurality of primary current outputs of the first primary current mirror (510), each of said plurality of secondary current mirrors (520) having a gain, and each of said plurality of secondary current mirrors (520) generating an inverted secondary current output signal, the magnitude of which is determined substantially by the unique one of the plurality of primary current outputs coupled thereto and the gain thereof.

Abstract: A selective call receiver (100) operates to recover an information signal and is capable of receiving a battery supplying a first voltage (203) that is multiplied to generate a second voltage (212). The selective call receiver (100) includes [comprises] a processor (106) that extracts message information contained within the recovered information signal for presentation and a power-on reset circuit (112) that generates a power-on reset signal having [comprising] first and second portions corresponding with a processor reset and a processor execute state, respectively. The power-on reset signal changes from the processor reset to the processor execute state when the second voltage (212) exceeds a sum of a PMOS threshold voltage and a NMOS threshold voltage, thereby completing a power-on reset of the processor (106).

Abstract: A class AB transconductance amplifier (200) has first and second differential input amplifier stages (100-112) adapted for receiving first and second differential input signals (Vin+, Vin-). First and second input cascode stages are coupled to the first and second differential input amplifier stages for providing first and second differential folded cascode signals. An output stage (113-118) is coupled to the first and second differential folded cascode signals providing an output signal indicative of a difference between the first and second differential input signals (Vin+, Vin-). A bias stage (101, 102) is coupled to said first and second differential input amplifier stages (103-104, 105-106) and the first and second input cascode stages bias the first and second differential input amplifier stages (100-112) to operate as a class AB folded cascode amplifier circuit (200). The bias stage generates class AB biasing signals.

Abstract: A method for full duplex data transference between a master device and a slave device comprises the steps of the slave device providing (725) data stored in a location within the slave device to the master device and the master device providing (760) modified data to be stored in the location to the slave device. A further step includes the slave device, substantially coincident with the master device providing (760) the modified data to the slave device, providing (755) data stored in a subsequent location within the slave device to the master device.

Abstract: An analog to digital converter (200, 300, 400) comprises a sink current circuit (200, 438, 440, 442) responsive to an input voltage for generating at least two sink currents. A source current circuit (300, 404, 406, 408, 418, 420, 422, 456, 458, 460) for generating at least three weighted source currents is coupled to the sink current circuit at summing nodes (424, 426, 428) in order to produce at least two digital output signals (D0, D1, D2). A switching circuit (444, 446, 448) is coupled to the source current circuit for enabling selected source currents in response to the digital output signals.

Abstract: A low power, dual mode BIMOS circuit generates a required drive voltage for illuminating an electroluminescent display panel from a low voltage, preferably a single cell. The BIMOS circuit comprises at least one bipolar transistor, at least one MOS transistor, an output voltage sensor, and a controller operating in a complementary fashion to disable a first clock signal coupled to the at least one bipolar transistor subsequent to enabling operation of the at least one MOS transistor for controlling the charging current used to generate the output voltage.

Abstract: A memory system for the non-volatile storage of digital information. The digital storage element is a semiconductor memory cell which is electrically erasable, readable, and programmable. There is a low voltage read mode provided to decrease system power requirements.

Abstract: An adaptive lock time controller for a phase locked loop having dividers for generating first and second loop timing signals, a phase detector, a voltage controlled oscillator, and a charging circuit for generating at least a first control signal for converging the output frequency to one or more predetermined frequency channels and a second control signal for maintaining the output frequency substantially constant, comprises a synchronization generator, a phase lock detector, and a control signal selector. The synchronization generator is responsive to the phase detector for synchronizing the phase lock detector. The phase lock detector detects phase locked and unlocked conditions by generating a count representative of the phase difference between the first and second loop timing signals. When the count generated exceeds a predetermined count, a phase locked condition exists, otherwise the loop is unlocked.

Abstract: A built in test circuit within a frequency synthesizer for use in selective call radio receivers provides a selectable one of a plurality of internal signals as a test signal for diagnosing the frequency synthesizer's output in real time.

Abstract: An apparatus for determining if a received binary word corresponds to the true or complement version of a stored binary word includes means for serially multiplexing the bits of each binary word to the inputs of an exclusive OR gate. The exclusive-OR gate generates a logical high signal each time a mismatch occurs. These signals are applied directly to an error counter and, after inversion, to a match counter. The contents of the error counter and match counter are compared to a stored threshold number. A first signal is generated if the contents of the error counter exceeds the threshold. A second signal is generated if the contents of the match counter exceeds the threshold. Upon the occurrence of both signals, the serial comparison process is terminated.