Abstract: Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

Abstract: A structure for implementation of back-illuminated CMOS or CCD imagers. An epitaxial silicon layer is connected with a passivation layer, acting as a junction anode. The epitaxial silicon layer converts light passing through the passivation layer and collected by the imaging structure to photoelectrons. A semiconductor well is also provided, located opposite the passivation layer with respect to the epitaxial silicon layer, acting as a junction cathode. Prior to detection, light does not pass through a dielectric separating interconnection metal layers.

Abstract: A method for implementation of back-illuminated CMOS or CCD imagers. An oxide layer buried between silicon wafer and device silicon is provided. The oxide layer forms a passivation layer in the imaging structure. A device layer and interlayer dielectric are formed, and the silicon wafer is removed to expose the oxide layer.

Abstract: The present invention provides a CMOS imager with a reset scheme, by which a CMOS imager generates a sub-kTC noise so that read noise does not depend on the sense node capacitance. By using a column feedback circuit, reset noise can be suppressed to a negligible amount so that photogate APS or CCD-like circuits can achieve noise performance to very efficient value. This scheme allows increasing sense node capacitance without increasing the noise and also achieves a large full-well value without sacrificing read noise performance. The feedback circuit in one of the embodiment of the present invention is located at the column side of the circuit. This design provides a minimal change to the pixel. As a result quantum efficiency or pixel size is not compromised. The present invention allows a CMOS imager to capture scene with high intra-scene contracts under low illumination with high dynamic range.

Abstract: An image sensor includes pixels formed on a semiconductor substrate. Each pixel includes a photoactive region in the semiconductor substrate, a sense node, and a power supply node. A first electrode is disposed near a surface of the semiconductor substrate. A bias signal on the first electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the sense node. A second electrode is disposed near the surface of the semiconductor substrate. A bias signal on the second electrode sets a potential in a region of the semiconductor substrate between the photoactive region and the power supply node.

Abstract: A multiple-step reset process and circuit for resetting a voltage stored on a photodiode of an imaging device. A first stage of the reset occurs while a source and a drain of a pixel source-follower transistor are held at ground potential and the photodiode and a gate of the pixel source-follower transistor are charged to an initial reset voltage having potential less that of a supply voltage. A second stage of the reset occurs after the initial reset voltage is stored on the photodiode and the gate of the pixel source-follower transistor and the source and drain voltages of the pixel source-follower transistor are released from ground potential thereby allowing the source and drain voltages of the pixel source-follower transistor to assume ordinary values above ground potential and resulting in a capacitive feed-through effect that increases the voltage on the photodiode to a value greater than the initial reset voltage.

Abstract: An imaging system for identifying the location of the center of mass (“COM”) in an image. In one aspect, an imaging system includes a plurality of photosensitive elements arranged in a matrix. A center of mass circuit coupled to the photosensitive elements includes a resistive network and a normalization circuit including at least one bipolar transistor. The center of mass circuit identifies a center of mass location in the matrix and includes: a row circuit, where the row circuit identifies a center of mass row value in each row of the matrix and identifies a row intensity for each row; a horizontal circuit, where the horizontal circuit identifies a center of mass horizontal value; and a vertical circuit, where the vertical circuit identifies a center of mass vertical value. The horizontal and vertical center of mass values indicate the coordinates of the center of mass location for the image.

Abstract: A two-dimensional range-imaging system is capable of transmitting light from a source into a field of view and focusing return portions of the light, reflected off targets in the field of view, onto a two-dimensional array of photodetectors. The photodectectors convert the return portions of light into electric signals that are compatible with a solid state circuit. Each electric signal is combined with a one or more reference signals to indicate a distance between the source and an associated target.

Abstract: Hardware circuit for median calculation in an active pixel sensor.

Abstract: A leakage compensated snapshot imager provides a number of different aspects to prevent smear and other problems in a snapshot imager. The area where the imager is formed may be biased in a way that prevents photo carriers including electrons and holes from reaching a storage area. In addition, a number of different aspects may improve the efficiency. The capacitance per unit area of the storage area may be one, two or more orders of magnitude greater than the capacitance per-unit area of the photodiode. In addition, a ratio between photodiode capacitance and storage area capacitance is maintained larger than 0.7.

Abstract: Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted.

Abstract: A vision system is disclosed. The system includes a pixel array, at least one multi-resolution window operation circuit, and a pixel averaging circuit. The pixel array has an array of pixels configured to receive light signals from an image having at least one tracking target. The multi-resolution window operation circuits are configured to process the image. Each of the multi-resolution window operation circuits processes each tracking target within a particular multi-resolution window. The pixel averaging circuit is configured to sample and average pixels within the particular multi-resolution window.

Abstract: The present invention relates to a system and method for performing rapid and programmable analysis of data. The present invention relates to a reconfigurable detector comprising at least one array of a plurality of pixels, where each of the plurality of pixels can be selected to receive and read-out an input. The pixel array is divided into at least one pixel group for conducting a common predefined analysis. Each of the pixels has a programmable circuitry programmed with a dynamically configurable user-defined function to modify the input. The present detector also comprises a summing circuit designed to sum the modified input.

Abstract: An imager that is better suited for low-light detection capability. In accordance with a preferred embodiment, the imager may be easily configured to provide an imager having multi-resolution capability where SNR can be adjusted for optimum low-level detectibility. Multi-resolution signal processing functionality is provided on-chip to achieve high speed imaging, as well as low power consumption. The imager architecture employs an improved pixel binning approach with fully differential circuits situated so that all extraneous and pick-up noise is eliminated. The current implementation requires no frame transfer memory, thereby reducing chip size. The reduction in area enables larger area format light adaptive imager implementations.

Abstract: An image sensor operable to vary the output spatial resolution according to a received light level while maintaining a desired signal-to-noise ratio. Signals from neighboring pixels in a pixel patch with an adjustable size are added to increase both the image brightness and signal-to-noise ratio. One embodiment comprises a sensor array for receiving input signals, a frame memory array for temporarily storing a full frame, and an array of self-calibration column integrators for uniform column-parallel signal summation. The column integrators are capable of substantially canceling fixed pattern noise.

Abstract: The present invention provides a CMOS imager with a reset scheme, by which a CMOS imager generates a sub-kTC noise so that read noise does not depend on the sense node capacitance. By using a column feedback circuit, reset noise can be suppressed to a negligible amount so that photogate APS or CCD-like circuits can achieve noise performance to very efficient value. This scheme allows increasing sense node capacitance without increasing the noise and also achieves a large full-well value without sacrificing read noise performance. The feedback circuit in one of the embodiment of the present invention is located at the column side of the circuit. This design provides a minimal change to the pixel. As a result quantum efficiency or pixel size is not compromised. The present invention allows a CMOS imager to capture scene with high intra-scene contracts under low illumination with high dynamic range.

Abstract: A centroid computation system is disclosed. The system has an imager array, a switching network, computation elements, and a divider circuit. The imager array has columns and rows of pixels. The switching network is adapted to receive pixel signals from the image array. The plurality of computation elements operates to compute inner products for at least x and y centroids. The plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network. The divider circuit is adapted to receive the inner products and compute the x and y centroids.

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Abstract: Systems and techniques to realize pointing and tracking applications with CMOS imaging devices. In general, in one implementation, the technique includes: sampling multiple rows and multiple columns of an active pixel sensor array into a memory array (e.g., an on-chip memory array), and reading out the multiple rows and multiple columns sampled in the memory array to provide image data with reduced motion artifact. Various operation modes may be provided, including TDS, CDS, CQS, a tracking mode to read out multiple windows, and/or a mode employing a sample-first-read-later readout scheme. The tracking mode can take advantage of a diagonal switch array. The diagonal switch array, the active pixel sensor array and the memory array can be integrated onto a single imager chip with a controller. This imager device can be part of a larger imaging system for both space-based applications and terrestrial applications.

Abstract: A totally digital single chip camera includes communications to operate most of its structure in serial communication mode. The digital single chip camera include a D/A converter for converting an input digital word into an analog reference signal. The chip includes all of the necessary circuitry for operating the chip using a single pin.