Abstract: The claimed subject matter can provide a mechanism for ascertaining a variety of metrological data relating to one or more features (e.g., a transistor gate) of a chip/wafer. In addition, results of electrical testing on the chip/wafer can also be gathered and, together with the metrological data, input to a data store. From the information in the data store, a three-dimensional model for the feature(s) of the chip/wafer can be constructed and subjected to analysis, testing, and/or simulation. As well, the three-dimensional model can be optimized and an optimized three-dimensional model can be employed to affect process control in a feedback/forward manner, e.g., to apply optimizations to the next or the current wafer, respectively. Accordingly, the disclosed mechanisms may be used to optimize semiconductor performance, yield, or for research and development. In addition the three-dimensional model may be used in analysis, simulation, or debugging software.

Abstract: The claimed subject matter can provide a mechanism for ascertaining a variety of metrological data relating to one or more features (e.g., a transistor gate) of a chip/wafer. In addition, results of electrical testing on the chip/wafer can also be gathered and, together with the metrological data, input to a data store. From the information in the data store, a three-dimensional model for the feature(s) of the chip/wafer can be constructed and subjected to analysis, testing, and/or simulation. As well, the three-dimensional model can be optimized and an optimized three-dimensional model can be employed to affect process control in a feedback/forward manner, e.g., to apply optimizations to the next or the current wafer, respectively. Accordingly, the disclosed mechanisms may be used to optimize semiconductor performance, yield, or for research and development. In addition the three-dimensional model may be used in analysis, simulation, or debugging software.

Abstract: A system for optimizing critical dimension uniformity in semiconductor manufacturing processes is provided. The system comprises a bake plate simulator to model a physical bake plate. A finite element analysis engine uses information from the bake plate simulator to calculate missing information. A lithography simulator predicts outcomes of a lithography process using information from the bake plate simulator and the finite element analysis engine. The system can be used in a predictive capacity or as part of a process control system.

Abstract: A system that facilitates extraction of line edge roughness measurements that are independent of proprietorship of a metrology device comprises a structure patterned onto silicon with known line edge roughness values associated therewith. A metrology device obtains line edge roughness measurements from the structure, and a correcting component generates an inverse function based upon a comparison between the known line edge roughness values and the measured line edge roughness values. The metrology device can thereafter measure line edge roughness upon a second structure patterned on the silicon, and the inverse function can be applied to such measured line edge roughness values to enable obtainment of line edge roughness measurements that are independent of proprietorship of the metrology device.

Abstract: The disclosure provides methods to mitigate and/or eliminate problems associated with removal of carbon-based resists from organic low k dielectrics. The methods include forming an organic low k dielectric layer over a semiconductor substrate, forming a capping layer over the organic low k dielectric layer, forming a silicon-containing resist over the capping layer, patterning the silicon-containing resist layer to expose portions of the capping layer and to form a patterned silicon oxide layer, removing the organic low k dielectric layer to form one or more openings, and removing the patterned silicon oxide layer. The silicon-containing resist facilitates efficient patterning of the organic low k-dielectric layers, and thereby increases the performance and cost-effectiveness of semiconductor devices fabricated using organic low k dielectrics.

Abstract: A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold.

Abstract: The present invention is directed towards a system and/or methodology that facilitates controlling routing of blocks on a floor plan in an integrated circuit. A pattern collector receives a partially created routing pattern, and a comparing component makes a comparison between the at least partially created routing pattern with one or more patterns in a library of patterns. Routing is controlled based at least in part upon the comparison.

Abstract: Systems and methodologies are provided that account for surface variations of a wafer by adjusting grating features of an imprint lithography mask. Such adjustment employs piezoelectric elements as part of the mask, which can change dimensions (e.g., a height change) and/or move when subjected to an electric voltage. Accordingly, by regulating the amount of electric voltage applied to the piezoelectric elements a controlled expansion for such elements can be obtained, to accommodate for topography variations of the wafer surface.

Abstract: Disclosed are systems and methods that employ a structural framework of cell gratings placed on a wafer surface during an immersion lithography process to restrict motion of the immersion fluid. Thus, when the stepper lens comes in contact with the immersion fluid, a typically stable immersion fluid dynamics can be maintained with the cells during the immersion lithography process. In addition, various monitoring and control systems are employed to regulate stability of the immersion fluid.

Abstract: Disclosed are immersion lithography methods and systems involving irradiating a photoresist through a lens and an immersion liquid of an immersion lithography tool, the immersion liquid in an immersion space contacting the lens and the photoresist; removing the immersion liquid from the immersion space; charging the immersion space with a supercritical fluid; removing the supercritical fluid from the immersion space; and charging the immersion space with immersion liquid.

Abstract: Systems and method for adjusting an etch rate of an organic bottom antireflective coating (BARC) layer on a wafer. The BARC layer can be exposed to an energy source at varied intensities to determine a relationship between bake temperature and solubility of the BARC after baking, which correlates to a rate at which the BARC can be etched. The BARC can be a cross-linking BARC, which becomes more cross-linked as bake temperature is increased, resulting in decreased etch rate, or can be a cleaving BARC, which is subject to removal of etch-resistant monomers as bake temperature is increased, resulting in increased etch rate. Thus, the invention provides for adjustable BARC etch rates that can be aligned to an etch rate of a photoresist deposited over the BARC to permit concurrent etching of both layers while mitigating structural defects that can occur if etch rates of the respective layers differ.

Abstract: A system and method are provided for detecting contaminants or defects on a reticle in-situ. The system and method provide a system that measures the optical transmission through clear areas on a reticle and determines whether the optical transmission of a reticle has been degraded by contaminants or other defects.

Abstract: Systems and methods are described that facilitate verifying that bottom apertures in tapered vias are open and free of obstruction. Scatterometry can be employed to monitor tapered via formation during and/or after a dry etch process on a photoresist bilayer. Information regarding critical dimensions at the bottoms of tapered vias can be analyzed to assess whether bottom apertures exhibit a minimum acceptable diameter that is equal to or greater than a predetermined threshold tolerance. Via apertures with dimensions below the threshold tolerance and/or regions of a wafer evincing unacceptable frequent occurrences of faulty via apertures are considered occluded, or suspect, and a corrective re-etch can be performed thereon.

Abstract: A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold.

Abstract: A system and method for detecting bubbles in a lithographic immersion medium and for controlling a lithographic process based at least in part on the detection of bubbles is provided. A bubble monitoring component emits an incident beam that passes through the immersion medium and is incident upon a substrate to produce a reflected and/or diffracted beam(s). The reflected and/or diffracted beam(s) is received by one or more optical detectors. The presence or absence of bubbles can be derived from information extracted by scatterometry from the reflected and/or diffracted beams. A process control component interacts with a positioning component and an optical exposure component to alter a lithographic process based at least in part on the results of the scatterometry.

Abstract: Systems and/or methods are disclosed for aligning multiple layers of a multi-layer semiconductor device fabrication process and/or system utilizing a composite alignment mark. A component is provided to form the composite alignment mark, such that a first portion of the composite alignment mark is associated with a layer of the wafer and a second portion of the composite alignment mark is associated with a disparate layer of the wafer. An alignment component is utilized to align a reticle for a layer to be patterned to the composite alignment mark.

Abstract: The subject invention provides a system and method for improving the process margin of a lithographic imaging system. The process margin improvement is achieved through the novel placement of discrete assist features and/or the use of forbidden pitches and specific pitch orientations. Novel geometries are utilized, which take advantage of line-end pull back and/or a lack of resolution of pitches perpendicular to an axis of a dipole illumination source. The strategic placement of a series of discrete scatterbar segments on a mask near positions of critical features, such as, for example, contacts, mitigates resist residue that can result from the use of a contiguous scatterbar.

Abstract: The present invention relates to monitoring and controlling a reticle fabrication process (e.g. employed with an electron beam lithography process). A typical fabrication process involves discrete stages including exposure, post-exposure bake and development. After fabrication is complete, an inspection can be performed on the reticle to determine whether any parameters during fabrication and/or any data points are outside of acceptable tolerances. The data is collected and fed into an algorithm (e.g. data-mining algorithm) utilized to determine which fabrication parameters need to be modified then sends the data to a control system (e.g. advanced process control) to facilitate needed changes to the fabrication parameters.

Abstract: The present invention relates to visually monitoring an interior portion of a processing chamber in a semiconductor processing system. An image collector collects images of the interior of the chamber and provides an image signal indicative of a visual representation of the interior of the chamber. A viewing station receives the image signal and displays a visual representation of the interior of the chamber.

Abstract: Disclosed are immersion lithography methods and systems involving irradiating a photoresist through a lens and an immersion liquid of an immersion lithography tool, the immersion liquid in an immersion space contacting the lens and the photoresist; removing the immersion liquid from the immersion space; charging the immersion space with a supercritical fluid; removing the supercritical fluid from the immersion space; and charging the immersion space with immersion liquid.