Abstract: Systems and/or methods are disclosed for measuring and/or controlling an amount of impurity that is dissolved within an immersion medium employed with immersion lithography. The impurity can be photoresist from a photoresist layer coated upon a substrate surface. A known grating structure is built upon the substrate. A real time immersion medium monitoring component facilitates measuring and/or controlling the amount of impurities dissolved within the immersion medium by utilizing light scattered from the known grating structure.

Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate improved critical dimension (CD) control and the reduction of line-edge roughness (LER) during pattern line formation in an imprint mask. One aspect of the invention provides for forming features having CDs that are larger than ultimately desired in a mask resist. Upon application of a non-lithographic shrink technique, LER is mitigated and CD is reduced to within a desired target tolerance.

Abstract: Disclosed are immersion lithography methods involving irradiating a first photoresist through a lens and an immersion liquid, the immersion liquid contacting the lens and the first photoresist in a first apparatus; contacting the lens with a supercritical fluid in a second apparatus; and irradiating a second photoresist through the lens and an immersion liquid, the immersion liquid contacting the lens and the second photoresist in the first apparatus.

Abstract: A system and method are provided to facilitate dual damascene interconnect integration in a single imprint step. The method provides for creation of a translucent imprint mold with three-dimensional features comprising the dual damascene pattern to be imprinted. The imprint mold is brought into contact with a photopolymerizable organosilicon imaging layer deposited upon a transfer layer which is spin coated or otherwise deposited upon a dielectric layer of a substrate. When the photopolymerizable layer is exposed to a source of illumination, it cures with a structure matching the dual damascene pattern of the imprint mold. A halogen breakthrough etch followed by oxygen transfer etch transfer the vias from the imaging layer into the transfer layer. A second halogen breakthrough etch followed by a second oxygen transfer etch transfer the trenches from the imaging layer into the transfer layer. A dielectric etch transfers the pattern from the transfer layer into the dielectric layer.

Abstract: Methods of fabricating an integrated circuit on a wafer using dual mask exposure lithography is disclosed. Improved mask image alignment between a first mask image and a second mask image of a dual mask exposure technique can be achieved by aligning the second mask image to a latent image created by an exposure using the first mask image.

Abstract: The present invention relates generally to semiconductor processing, and more particularly to methods and systems for reducing costs of wafer production by analyzing key aspects of wafer status to determine whether to initiate corrective measures to salvage a wafer at an early stage and before substantial costs are incurred in fabricating a defective wafer. One aspect of the present invention provides for growing an oxide layer on a wafer upon a determination that an oxide layer on the wafer surface is absent or is present but inadequate. Another aspect of the present invention provides for a determination of whether to apply preemptory corrective treatment(s) to a wafer surface based on the presence and/or magnitude of nitrogen signatures in an extant oxide surface layer, which can indicate that an undesirable defect known as “footing” will occur during a post-exposure delay period.

Abstract: A system for performing inventory control for wafers, unpackaged integrated circuits and packaged integrated circuits is provided. The system includes barcode readers, sorters and transporters operable to locate and relocate wafers, unpackaged circuits and packaged circuits. The system further includes a feedback system for feeding back information generated by the barcode readers, sorters, transporters and/or manufacturing devices associated with the wafers, unpackaged circuits and packaged circuits. The system further provides for generating Electronic Data Interchange (EDI) data that can be transmitted to wafer suppliers and employed in controlling wafer ordering, purchasing, processing and returning.

Abstract: A system and method for monitoring the creation of semiconductor features with multi-slope profiles by employing scatterometry is provided. The system includes a wafer partitioned into one or more portions and one or more light sources, each light source directing light to one or more devices etched on a wafer, the devices having multi-sloped profiles. Reflected light is collected and converted into data by a measuring system. The data is indicative of the etching at the one or more portions of the wafer. The measuring system provides the data to a process analyzer that determines whether adjustments to etching components are necessary by comparing the data to stored etch parameter values. The system also includes etching components. At least one etch component corresponds to a portion of the wafer and performs the etching thereof. The process analyzer selectively controls the etch components to promote consistent etching of multi-slope profiles/features to compensate for wafer to wafer variations.

Abstract: A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. One or more structures formed on a wafer matriculating through the process facilitate concurrent measurement of critical dimensions and overlay via scatterometry or a scanning electron microscope (SEM). The concurrent measurements mitigate fabrication inefficiencies, thereby reducing time and real estate required for the fabrication process. The measurements can be utilized to generate feedback and/or feed-forward data to selectively control one or more fabrication components and/or operating parameters associated therewith to achieve desired critical dimensions and to mitigate overlay error.

Abstract: A system for monitoring and controlling the deposition of thin films employed in semiconductor fabrication is provided. The system includes one or more acoustic and/or ultrasonic wave sources, each source directing waves onto one or more thin films deposited on a wafer. Waves reflected from the thin film is collected by a monitoring system, which processes the collected waves. Waves passing through the thin film may similarly be collected by the monitoring system, which processes the collected waves. The collected waves are indicative of the presence of impurities and/or defects in the deposited thin film. The monitoring system analyzes and provides the collected wave data to a processor, which determines whether adjustments to thin film deposition parameters are needed. The system also includes a plurality of thin film deposition devices associated with depositing thin films on the wafer. The processor selectively controls thin film deposition parameters and devices to facilitate regulating deposition.

Abstract: One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.

Abstract: Systems and methods that improve process control in semiconductor manufacturing are disclosed. According to an aspect of the invention, conditions in a cluster tool environment and/or a wafer therein can be monitored in-situ via, for example, a scatterometry system, to determine whether parameters associated with wafer production are within control limits. A cluster tool environment can include, for example, a lithography track, a stepper, a plasma etcher, a cleaning tool, a chemical bath, etc. If an out-of-control condition is detected, either associated with a tool in the cluster tool environment or with the wafer itself, compensatory measures can be taken to correct the out-of-control condition. The invention can further employ feedback/feed-forward loop(s) to facilitate compensatory action in order to improve process control.

Abstract: The present invention generally relates to semiconductor processing, and in particular to methods and systems for analyzing photolithographic reticle defects that include detecting soft defects on a reticle and analyzing the material composition of the defects for a particular chemical signature. Specifically, the present invention scans and images a soft defect via an optical inspection scan of a reticle, mills the defect using a Focused Ion Beam, and analyzes the defect for signatures using Electron Spectroscopy for Chemical Analysis and/or Fourier Transform Infrared Spectroscopy. The present invention thus provides for real-time analysis of the chemical composition of a soft defect on a reticle without the need for a defect identification navigation system. According to an aspect of the present invention, reticle defects can be monitored without removal of a pellicle, thus facilitating increased throughput and decreased cost in reticle repair and/or cleaning.

Abstract: A system facilitating measurement and correction of overlay between multiple layers of a wafer is disclosed. The system comprises an overlay target that represents overlay between three or more layers of a wafer and a measurement component that determines overlay error existent in the overlay target, thereby determining overlay error between the three or more layers of the wafer. A control component can be provided to correct overlay error between adjacent and non-adjacent layers, wherein the correction is based at least in part on measurements obtained by the measurement component.

Abstract: The present invention relates generally to photolithographic systems and methods, and more particularly to systems and methodologies that facilitate the reduction of line-edge roughness (LER) and/or standing wave expression during pattern line formation in an integrated circuit. Systems and methods are disclosed for retaining a target critical dimension (CD) of photoresist lines, comprising a non-lithographic shrink component that facilitates mitigating LER and/or standing wave expression, wherein the shrink component is employed to heat a particular resist to the glass transition temperature of the resist to effectuate mitigation of LER and/or standing wave expression. Additionally, by heating the resist to its glass transition temperature, the systems and methods of the present invention effectively impede deviation from a desired target critical dimension.

Abstract: A multi-layer immersion medium monitoring system for a lithographic process monitors characteristics of an immersion medium of a semiconductor manufacturing process. The multi-layer immersion medium includes at least a first liquid of a first density (or viscosity) and a second liquid of a lower density (or viscosity), both of which are interspersed between a final optical component and a semiconductor layer. The higher density layer is provided to reduce turbulence in the immersion medium during the lithographic processes. A scatterometry system monitors optical characteristics of the multi-layer immersion medium to effectuate control of a lithographic process.

Abstract: Disclosed are immersion lithography methods involving using a base developer as an immersion lithography fluid. Consequently, it is unnecessary to contact a developer with an irradiated resist after the immersion lithography fluid is removed.

Abstract: A system for regulating an etch process is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the acceptability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor selectively controls the etching devices to regulate etching of the portions of the wafer.

Abstract: The present invention uses in situ scatterometry to determine if a defect (e.g., photoresist erosion, photoresist bending and pattern collapse) is present on a wafer. In one embodiment, in situ scatterometry is used to detect a pattern integrity defect associated with the layer of photoresist. In situ scatterometry produces diffraction data associated with the thickness of the photoresist patterned mask. This data is compared to a model of diffraction data associated with a suitable photoresist thickness. If the measured diffraction data is within an acceptable range, the next step of the photolithography process is carried out. However, if the measured thickness is outside of the suitable range, a defect is detected, and the wafer may be sent for re-working or re-patterned prior to main etch, thereby preventing unnecessary wafer scrap.

Abstract: A damascene process can be utilized to form a T-shaped gate. A silicon rich nitride or SiON layer can be etched to form a first aperture. An oxide layer can be provided above the silicon rich nitride layer or SiON layer. A second aperture or trench can be provided in the oxide layer. The second trench can have a larger width than the trench in the silicon rich nitride layer or SiON layer. A gate conductor material, such as polysilicon, can be provided in the first trench and/or the second trench.