Abstract: The present invention relates to inspection methods and systems utilized to provide a best means for inspection of a wafer. The methods and systems include wafer-to-reticle alignment, layer-to-layer alignment and wafer surface feature inspection. The wafer-to-reticle alignment is improved by the addition of diagonal lines to existing alignment marks to decrease the intersection size and corresponding area that a desired point can reside. Layer-to-layer alignment is improved in a similar manner by the addition of oblique and/or non-linear line segments to existing overlay targets. Also, providing for wafer surface inspection in a multitude of desired diagonal axes allows for more accurate feature measurement.

Abstract: A system and/or method are disclosed for measuring and/or controlling refractive index (n) and/or lithographic constant (k) of an immersion medium utilized in connection with immersion lithography. A known grating structure is built upon a substrate. A refractive index monitoring component facilitates measuring and/or controlling the immersion medium by utilizing detected light scattered from the known grating structure.

Abstract: A microdevice for forming a part of an integrated circuit and method for fabricating are disclosed. The microdevice can include a first conductive region and a second conductive region having a channel region interposed therebetween. The mircodevice has a channel region controlling component disposed over the channel region and separated therefrom by at least one dielectric layer. The channel region controlling component has a non-linear structural characteristic derived from a non-linear structural characteristic of a photo resist feature used as an etch mask for the channel region controlling component.

Abstract: Disclosed are a system and method for monitoring a patterned photoresist clad-wafer structure undergoing an etch process. The system includes a semiconductor wafer structure comprising a substrate, one or more intermediate layers overlying the substrate, and a first patterned photoresist layer overlying the intermediate layers, the semiconductor wafer structure being etched through one or more openings in the photoresist layer; a wafer-etch photoresist monitoring system programmed to obtain data relating to the photoresist layer as the etch process progresses; a pattern-specific grating aligned with the wafer structure and employed in conjunction with the monitoring system, the grating having at least one of a pitch and a critical dimension identical to the first patterned photoresist layer; and a wafer processing controller operatively connected to the monitoring system and adapted to receive data from the monitoring system in order to determine adjustments to a subsequent wafer clean process.

Abstract: A photomask for use in a lithographic process and a method of making a photomask are disclosed. A mask blank including a substrate, a sacrificial conductive layer disposed over the substrate and a radiation shielding layer disposed over the sacrificial conductive layer can be provided. Structures are then formed from the radiation shielding layer to define a pattern. Measurement of parameters associated with the structures are made with a measurement tool and, during the measuring, the sacrificial conductive layer provides a conductive plane to dissipate charge transferred to the mask by the measurement tool.

Abstract: A system for testing a reticle used in semiconductor wafer fabrication is provided. The system includes a reticle that has an opaque metal layer over a translucent substrate. The reticle includes one or more test features containing probe points operable for electrical contact. The system includes a reticle test system that is capable of applying a voltage to the probe points, measuring the resulting current, calculating the corresponding resistance of the test features, and determining the critical dimensions of the test features. The system is also capable of determining defects based on the resistance measurements. The critical dimension information and defect information can then be used to refine the processes used in the fabrication of subsequent reticles.

Abstract: Architecture for monitoring a bottom anti-reflective coating (BARC) undercut and residual portions thereof during a development stage using scatterometry. The scatterometry system monitors for BARC undercut and residual BARC material, and if detected, controls the process to minimize such effects in subsequent wafers. If one or more of such effects has exceeded a predetermined limit, the wafer is rerouted for further processing, which can include rework, etch back of the affected layer, or rejection of the wafer, for example.

Abstract: A system and method facilitating lithography defect solution generation is provided. The invention includes a defect solution component and a defect alert component. The defect solution component provides potential solution(s) to a defect within the lithography process utilizing artificial intelligence technique(s) (e.g., Bayesian learning methods that perform analysis over alternative dependent structures and apply a score, Bayesian classifiers and other statistical classifiers, including decision tree learning methods, support vector machines, linear and non-linear regression and/or neural network).

Abstract: A system facilitating measurement and correction of overlay between multiple layers of a wafer is disclosed. The system comprises an overlay target that represents overlay between three or more layers of a wafer and a measurement component that determines overlay error existent in the overlay target, thereby determining overlay error between the three or more layers of the wafer. A control component can be provided to correct overlay error between adjacent and non-adjacent layers, wherein the correction is based at least in part on measurements obtained by the measurement component.

Abstract: A system and methodology for monitoring and/or controlling a semiconductor fabrication process is disclosed. Scatterometry and/or ellipsometry based techniques can be employed to facilitate providing measurement signals during a damascene phase of the fabrication process. The thickness of layers etched away during the process can be monitored and one or more fabrication components and/or operating parameters associated with the fabrication component(s) can be adjusted in response to the measurements to achieve desired results, such as to mitigate the formation of copper oxide during etching of a copper layer, for example.

Abstract: A system for selectively generating and feeding forward reticle fabrication data is provided. The system includes components for fabricating a reticle and a control system operatively connected to the fabricating components, where the control system can control the operation of the fabricating components. The control system bases its control of the fabricating components, at least in part, on feed forward control information generated by a processor that analyzes scatterometry based reticle fabrication data gathered from measurement components. The scatterometry data is compared to data stored in a signature data store that facilitates analyzing gathered scatterometry signatures to produce feed forward control information that can be employed to manipulate subsequent reticle fabrication processes and/or apparatus.

Abstract: One aspect of the present invention relates to a system and method for controlling defect formation during a resist strip process. The system includes a reaction chamber comprising a patterned resist layer overlying a semiconductor structure wherein the resist layer is being exposed to a plasma material flowing into the chamber in order to facilitate removing the resist layer from the structure, a plasma-resist particle monitoring system connected to the reaction chamber and programmed to determine a particle count in the reaction chamber during the resist strip process, and a reaction controller coupled to the chamber and to the monitoring system, the reaction controller being programmed to receive particle data from the monitoring system to facilitate determining whether the counted particles in the chamber are within a tolerable limit. The method involves continuing to expose the structure and the chamber to the plasma until an acceptable particle count is obtained.

Abstract: The present invention provides systems and methods that facilitate performing fabrication process. Critical parameters are valued collectively as a quality matrix, which weights respective parameters according to their importance to one or more design goals. The critical parameters are weighted by coefficients according to information such as, product design, simulation, test results, yield data, electrical data and the like. The invention then can develop a quality index which is a composite “score” of the current fabrication process. A control system can then do comparisons of the quality index with design specifications in order to determine if the current fabrication process is acceptable. If the process is unacceptable, test parameters can be modified for ongoing processes and the process can be re-worked and re-performed for completed processes. As such, respective layers of a device can be customized for different specifications and quality index depending on product designs and yields.

Abstract: A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. Measurements are taken in accordance with scatterometry based techniques of repeating in circuit structures that evolve on a wafer as the wafer undergoes the fabrication process. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Additionally, the measurements can be employed in determining whether to discard the wafer or portions thereof based on a cost benefit analysis, for example. Directly measuring in circuit structures mitigates sacrificing valuable chip real estate as test grating structures may not need to be formed within the wafer, and also facilitates control over the elements that actually affect resulting chip performance.

Abstract: The present invention involves a method for fabricating interconnecting lines and vias. According to the invention, copper is grown within the openings in a patterned coating. The patterned coating can be a resist coating or a dielectric coating. Either type of coating can be formed over a copper seed layer, whereby the seed layer is exposed within the pattern gaps. The copper seed layer can also be provided within the pattern gaps after patterning. Copper features are grown within the pattern gaps by plating. Where the patterned coating is a resist, the resist is stripped leaving the copper features in the inverse pattern image. The copper features can be coated with a diffusion barrier layer and a dielectric. The dielectric is polished to leave the dielectric filling the spaces between copper features. The invention provides copper lines and vias without the need for a dielectric or metal etching step.

Abstract: The present invention provides a system and method for detecting and repairing defects in semiconductor devices. According to the invention, defects are located using a scanning probe microscope, such as an atomic force microscope or a scanning tunneling microscope, and repaired at locations determined by the scanning probe microscope. The microscope itself, and in particular the detection tip, may be employed to remove the defects. For example, the tip may be used to machine away the defect, to apply an electric field to oxidize the defect, and/or to heat the defect causing it to burn or vaporize. By combining precise defect location capabilities of a scanning probe microscope with defect removal, the invention permits very precise correction of defects such as excess material and foreign particles on semiconductor substrates.

Abstract: One aspect of the present invention relates to a method to facilitate formation of seed layer portions on sidewall surfaces of a trench formed in a substrate. The method involves the steps of forming a conformal seed layer over a barrier layer disposed conformal to a trench, wherein the trench is formed in the substrate; reflecting a light beam of x-ray radiation at the seed layer sidewall portions; generating a measurement signal based on the reflected portion of the light beam; and determining a thickness of the sidewall portions based on the measurement signal while the sidewall portions are being formed over the trench.

Abstract: One aspect of the present invention relates to a system and method for controlling an EUV mask fabrication process using a scatterometer. The system includes an EUV mask fabrication system comprising a translucent substrate having one or more layers of reflective material formed thereon and a patterned photoresist layer as the uppermost layer, a mask inspection system operatively connected to the mask fabrication system for examining the layers as they are being etched and developed by the mask fabrication system and generating data related thereto, and an EUV mask fabrication control system coupled to the mask inspection system for receiving data from the inspection system in order to regulate the mask fabrication system to facilitate obtaining desired critical dimensions. The method involves monitoring the etching of the features, generating data related to the features, and relaying the data to a control system to optimize the EUV mask fabrication process.

Abstract: A system comprised of a plurality of fabs that are operatively coupled and share data from a common framework for correlating production. The fabs can be coupled via Internet, cellular, optical, landline, microwave and satellite communication means and the like. Data can be transferred to and/or received from a central, integrated correlating entity or from several distributed correlating entities. The fabs send and receive correlating data that relates to production information such as tolerances, critical dimensions, geometry and the like. The correlating entity(s) has the capability to increase production by performing probabilistic computations on the received correlating data and utilizing the resulting information to maintain correlating parameters at remote locations. The computations performed can include such calculations as Bayesian inferencing and the like. The system inherently precludes the necessity for physically transporting parametric test entities between different fab or tooling locations.

Abstract: A method for forming a semiconductor device is described. The method comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. The BARC layer is exposed to an electron beam (e-beam) so that the BARC layer reaches a flow temperature in the at least one hole. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the BARC layer in the at least one hole acts as an etch resistant layer during the etch.