Abstract: A multi-layer PCB has conductive vias (134) passing through multiple layers. A layer may have a conductive non-functional feature (710) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad (310n).

Abstract: Embodiments described herein relate to a method for modifying transmission line characteristics. The method may include: making a first determination of a null frequency of an input signal to a transmission line; performing an analysis to make a second determination of a wavelength of the input signal using, at least in part, the null frequency; making a third determination, based on the analysis, of a half wavelength of the input signal; calculating, based on the half wavelength, a total stub length; and adding a trace to a stub associated with a via, wherein the stub and the trace are a length that is at least a portion of the half wavelength of the input signal.

Abstract: An information handling system includes a first Dual In-Line Memory Module (DIMM) on a first memory channel of the information handling system, and a second DIMM on a second memory channel of the information handling system. A processor trains the first memory channel to a first speed based upon a first performance level of the first DIMM, trains the second memory channel to a second speed based upon a second performance level of the second DIMM, and allocates a portion of the first DIMM to the application based upon the first speed.

Abstract: A dual axial cable includes first and second signal conductors and a shield. The first and second signal conductors transmit a differential signal. The shield includes a foil wrap spirally wrapped around the first and second conductors to form a plurality of foil wrap sections. Each of the foil wrap sections overlaps an adjacent foil wrap section. The periodicity of a pitch of each of the overlaps varies along a length of the dual axial cable.

Abstract: A system may include a transmitter, a receiver, a cable coupled between the transmitter and the receiver and having two wires for communicating a differential signal from the transmitter to the receiver, and a direct-current (DC) voltage source coupled to a first wire of the two wires of the cable and configured to apply a variable DC offset voltage to the first wire in order to vary an impedance of the cable as a function of the variable DC offset voltage.

Abstract: A system may include a transmitter, a receiver, a cable coupled between the transmitter and the receiver and having two wires for communicating a differential signal from the transmitter to the receiver, and a direct-current (DC) voltage source coupled to a first wire of the two wires of the cable and configured to apply a variable DC offset voltage to the first wire in order to vary an impedance of the cable as a function of the variable DC offset voltage.

Abstract: Embodiments described herein relate to a method for modifying transmission line characteristics. The method may include: making a first determination of a null frequency of an input signal to a transmission line; performing an analysis to make a second determination of a wavelength of the input signal using, at least in part, the null frequency; making a third determination, based on the analysis, of a half wavelength of the input signal; calculating, based on the half wavelength, a total stub length; and adding a trace to a stub associated with a via, wherein the stub and the trace are a length that is at least a portion of the half wavelength of the input signal.

Abstract: A dual axial cable includes first and second signal conductors and a shield. The first and second signal conductors transmit a differential signal. The shield includes a foil wrap spirally wrapped around the first and second conductors to form a plurality of foil wrap sections. Each of the foil wrap sections overlaps an adjacent foil wrap section. The periodicity of a pitch of each of the overlaps varies along a length of the dual axial cable.

Abstract: Embodiments described herein relate to a method for modifying transmission line characteristics. The method may include: making a first determination of a null frequency of an input signal to a transmission line; performing an analysis to make a second determination of a wavelength of the input signal using, at least in part, the null frequency; making a third determination, based on the analysis, of a half wavelength of the input signal; calculating, based on the half wavelength, a total stub length; and adding a trace to a stub associated with a via, wherein the stub and the trace are a length that is at least a portion of the half wavelength of the input signal.

Abstract: A printed circuit board includes a differential signal via pairs to route differential signal between layers of the printed circuit board. A first differential signal via pair is oriented in a first orientation and a second differential signal via pair is oriented perpendicular to the first orientation. The second differential signal via pair is located such that a midpoint of a first line segment drawn between centers of first and second vias of the second differential signal pair intersects a first ray drawn from a center of a first via of the first differential signal via pair through a center of a second via of the first differential signal via pair. Further, the second differential signal via pair is located such that the midpoint of the first line segment is at a characteristic via-to-via pitch distance for the printed circuit board from the center of the second via of the first differential signal via pair.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may determine a first height of a first eye diagram of a differential pair of circuit board traces of a circuit board of an information handling system; may determine a first width of the first eye diagram; may transfer a liquid above an area of the circuit board; may provide a differential signal to the differential pair; may determine a second height of a second eye diagram of the differential pair; may determine a second width of the second eye diagram; may determine at least one of that the second height is less than the first height by at least a first threshold and that the second width is less than the first width by at least a second threshold; and may provide information that indicates a presence of the liquid on the circuit board.

Abstract: A dynamic random access memory (DRAM) device includes an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller, and ODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device. The ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level.

Abstract: An information handling system includes a control processing unit (CPU) including a dual in-line memory module (DIMM) controller and hosting a basic input output system (BIOS). A first and a second set of DIMMs are connected to the CPU through the DIMM controller and by a first communication channel and a second communication channel, respectively. Each DIMM in the first and second set of DIMMs may be configured by the BIOS to include a unique data bus IO voltage (Vddq) setting for bidirectional communications with the CPU.

Abstract: An information handling system includes a control processing unit (CPU) including a dual in-line memory module (DIMM) controller and hosting a basic input output system (BIOS). A first and a second set of DIMMs are connected to the CPU through the DIMM controller and by a first communication channel and a second communication channel, respectively. Each DIMM in the first and second set of DIMMs may be configured by the BIOS to include a unique data bus IO voltage (Vddq) setting for bidirectional communications with the CPU.

Abstract: A method includes training an artificial neural network with training data that comprises a sets of design parameter values for design parameters for circuit traces in a high speed communication link, determining an output formula that relates a sets of design parameters to a corresponding output parameter for the circuit traces in response to training the artificial neural network, running the output formula using a second set of design parameter values to obtain a corresponding set of output parameters for the circuit traces, determining that the corresponding set of output parameters differ from a set of modeled output parameters by less than a predefined percentage, and fabricating a circuit trace in a printed circuit board based upon the output formula in response to determining that the corresponding set of output parameters differ from the set of modeled output parameters by less than the predefined percentage.

Abstract: A differential trace pair system includes a board including a board structure having a first, a second, a third, and a fourth board structure member, wherein a distance between the first and the third board structure members is longer than a distance between the second and the fourth board structure members. The differential trace pair system further includes a differential trace pair that includes a first differential trace extending between the first and the third board structure members and a second differential trace extending between the second and the fourth board structure members. The second differential trace having a serpentine structure that includes a first portion that continuously transitions away from the first differential trace and a second portion that is contiguous with the first portion, the second portion continuously transitions towards the first differential trace.

Abstract: A memory device failure recovery system includes a memory device management engine that is coupled to a first memory device via a first memory device slot, and a memory device management database. The memory device management engine identifies that the first memory device has experienced a failure in a configuration region of the first memory device during a current boot operation and, in response, retrieves memory device component information and memory device configuration information that is stored in the memory device management database and that was retrieved as part of a prior boot operation from a memory device that was connected to the first memory device slot. During the current boot operation, the memory device management engine determines whether first memory device components on the first memory device correspond to the memory device component information and, if so, uses the memory device configuration information to configure the first memory device.

Abstract: A printed circuit board (PCB) for an information handling system includes first and second signal vias, and a quantity of ground vias. The first signal via is separated from the second signal via by a first distance. The ground vias are grouped into pairs and each ground via of each pair is separated from one of the first or second signal vias by a second distance. The location of the ground vias in terms of an angle between the ground vias is given as an expression relating the first distance, the second distance, and the quantity of ground vias.

Abstract: A flat flexible cable may include a plurality of generally parallel, co-planar flat conductive traces sandwiched between two ribbons of dielectric material and a plurality of strips of conductive material formed at intervals along a length of the flat flexible cable, each strip of conductive material electrically coupling a plurality of ground traces of the flat conductive traces to one another via portions of the ground traces exposed through the dielectric material at each of the intervals.

Abstract: A printed circuit board includes first and second signal pads, and first, second, and third ground pads. The first and second signal pads and the first and second ground pads are arranged in a line with the first and second signal pads between the first and second ground pads. The third ground pad is arranged between the first and second signal pads but is not in line with the first and second signal pads.