Abstract: An electrical connector element, for use on a printed circuit board assembly, includes a soldering pad having a longitudinal length and a cross-sectional width. The soldering pad is configured to be electrically-coupleable to a PCB device conductor. At least one impedance inducing feature is positioned along the longitudinal length of the soldering pad.

Abstract: A signal trace on a printed circuit board (PCB) includes a first trace segment on a first layer of the PCB, the first trace segment having a first end coupled to a transmitter, having a second end, and having a first characteristic impedance that is matched to the transmitter. The signal trace further includes a signal via passing from the first layer of the PCB to a second layer of the PCB, the signal via having a first contact connected to the second end of the first trace segment, having a second contact on the second layer, and having a second characteristic impedance different from the first characteristic impedance. The second characteristic impedance is determined based upon a first distance between the transmitter and the first via.

Abstract: A differential trace pair system includes a board having a first, a second, a third, and a fourth board structure member. A differential trace pair in the board includes a first differential trace extending between the first and the third board structure members, and a second differential trace extending between the second and the fourth board structure members. The differential trace pair includes a serpentine region that includes a first portion and a second portion where the first and the second differential traces have a first width, are substantially parallel, and spaced apart by a first differential trace pair spacing, and a third portion in which the second differential trace includes a second width that is greater than the first width, the first and second differential traces are substantially parallel and spaced apart by a second differential trace pair spacing that is greater than the first differential trace pair spacing.

Abstract: A memory device failure recovery system includes a memory device management engine that is coupled to a first memory device via a first memory device slot, and a memory device management database. The memory device management engine identifies that the first memory device has experienced a failure in a configuration region of the first memory device during a current boot operation and, in response, retrieves memory device component information and memory device configuration information that is stored in the memory device management database and that was retrieved as part of a prior boot operation from a memory device that was connected to the first memory device slot. During the current boot operation, the memory device management engine determines whether first memory device components on the first memory device correspond to the memory device component information and, if so, uses the memory device configuration information to configure the first memory device.

Abstract: A multi-layer PCB has conductive vias (134) passing through multiple layers. A layer may have a conductive non-functional feature (710) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad (310n).

Abstract: A circuit board pad connector system includes a connector that is configured to mount to a connector pad that is included on a circuit board. The connector includes a connector lead frame. A lead portion is provided on the connector lead frame such that the lead portion is oriented substantially perpendicularly relative to the connector pad when the connector is mounted to the connector pad. A first mounting portion is provided on the connector lead frame, is configured to mount the connector to the connector pad, and extends in a first direction that is substantially perpendicular relative to the lead portion. A second mounting portion is provided on the connector lead frame, is configured to mount the connector to the connector pad, and extends in a second direction that is different than the first direction and that is substantially perpendicular relative to the lead portion.

Abstract: An information handling system with enhanced receiver equalization may include a processing unit with a dual in-line memory module (DIMM) controller. The DIMM controller is connected to a first DIMM and a second DIMM by a communication channel. A basic input/output system is configured to set an equalization of a data signal on the communication channel by applying a first equalization to a Nyquist frequency that is associated with a data rate of the data signal and by applying a second equalization to a standing wave reflection frequency that is associated with an additional loading in the communication channel. The additional loading may be due to presence of another DIMM in the same communication channel.

Abstract: A printed circuit board (PCB) includes a plurality of layers and electronic components connected to its top surface. The PCB also includes a plurality of trace layers, each located at a respective depth within the layers of the PCB. A plurality of vias provide signal pathways for the trace layer. Upon their manufacture, the vias include a stub portion not necessary for the signal pathways and causing degradation of the integrity of these signal pathways. Embodiments mill the bottom of the PCB to form a variable-depth cavity. The different milling depths of the variable-depth cavity are selected to remove the stub portions of the plurality of vias and the dielectric material between the stubs. By configuring the PCB power planes as the topmost trace layers, decoupling capacitors may be located at the greatest depth of the variable-depth cavity, thus reducing the loop inductance in the power circuit of the PCB.

Abstract: A printed circuit board includes a circuit trace and a connector pad. The connector pad provides electrical and mechanical mounting of a connector lead of a surface mount device and provides a circuit path between the surface mount device and the circuit trace. The connector pad includes 1) a connector pad base electrically coupled to the circuit trace, and 2) a first connector pad island electrically isolated from the connector pad base. The connector pad base has a length that is substantially equal to a length of a contact portion of the connector lead.

Abstract: A multi-layer PCB has conductive vias (134) passing through multiple layers. A layer may have a conductive non-functional feature (710) physically contacting a via but not surrounding the via, to make the PCB more resistant to thermal stresses while, at the same time, reducing the parasitic capacitance compared to a prior art non-functional pad (310n).

Abstract: A signal trace on a printed circuit board (PCB) includes a first trace segment on a first layer of the PCB, the first trace segment having a first end coupled to a transmitter, having a second end, and having a first characteristic impedance that is matched to the transmitter. The signal trace further includes a signal via passing from the first layer of the PCB to a second layer of the PCB, the signal via having a first contact connected to the second end of the first trace segment, having a second contact on the second layer, and having a second characteristic impedance different from the first characteristic impedance. The second characteristic impedance is determined based upon a first distance between the transmitter and the first via.

Abstract: A printed circuit board includes first and second signal pads, and first, second, and third ground pads. The first and second signal pads and the first and second ground pads are arranged in a line with the first and second signal pads between the first and second ground pads. The third ground pad is arranged between the first and second signal pads but is not in line with the first and second signal pads.

Abstract: A printed circuit board (PCB) for an information handling system includes first and second signal vias, and a quantity of ground vias. The first signal via is separated from the second signal via by a first distance. The ground vias are grouped into pairs and each ground via of each pair is separated from one of the first or second signal vias by a second distance. The location of the ground vias in terms of an angle between the ground vias is given as an expression relating the first distance, the second distance, and the quantity of ground vias.

Abstract: An information handling system includes a processing unit that is coupled to a memory device by a communication channel. The processing unit includes a memory controller and is configured to host a basic input output system (BIOS). The memory device, which may include a dual in-line memory module (DIMM), stores serial presence detect (SPD) information. In an embodiment, the BIOS obtains the SPD information and parameters of the communication channel, such as channel impedance and channel length. In this embodiment, the BIOS uses a look-up table to determine an equalization of the communication channel based on the obtained SPD information and the obtained parameters of the communication channel, and utilizes the memory controller to set the equalization of the communication channel, such as by setting or controlling settings of transmission and reception components of the memory controller.

Abstract: A circuit board pad resonance control system includes a board. A signal transmission line is included on the board. A plurality of connector pads are positioned on the board. A first connector pad receives the signal transmission line adjacent a first end of that connector pad. The first connector pad includes a mounting surface that mounts directly to a coupling element that is configured to couple a subsystem to the board, and reduces a resonance that is produced by an open portion of a signal transmission path that is created when the coupling element is directly mounted to the mounting surface of the first connector pad in a first orientation. In a specific example, the mounting surface may include a plurality of protrusions, a plated surface, and/or a mask that reduces the conductivity of the connector pad which reduces signal integrity issues due to resonance.

Abstract: An information handling system may include a central processing unit (CPU) and a device. The CPU may have an I/O system and be configured to host a BIOS. The device may be communicatively connected to the I/O system of the CPU by a connection. The BIOS may determine a communication protocol used by the device for communication and set an equalization of the I/O system for communication with the device based on the communication protocol used by the device.

Abstract: A dynamic random access memory (DRAM) device includes an on-die termination (ODT) controller including an input to receive an ODT signal from a memory controller, and ODT circuitry to terminate an interface circuit, the interface circuit to provide a data signal between the memory controller and the DRAM device. The ODT controller is configured in a first impedance switching mode to terminate the interface circuit at a first impedance level in response to a first state of the ODT signal, to terminate the interface circuit at a second impedance level in response to a second state of the ODT signal, and to terminate the interface circuit at a third impedance level in response to a change in the ODT signal from the first state to the second state, the third impedance level being between the first impedance level and the second impedance level.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may determine a first height of a first eye diagram of a differential pair of circuit board traces of a circuit board of an information handling system; may determine a first width of the first eye diagram; may transfer a liquid above an area of the circuit board; may provide a differential signal to the differential pair; may determine a second height of a second eye diagram of the differential pair; may determine a second width of the second eye diagram; may determine at least one of that the second height is less than the first height by at least a first threshold and that the second width is less than the first width by at least a second threshold; and may provide information that indicates a presence of the liquid on the circuit board.

Abstract: A differential trace pair system includes a board including a board structure having a first, a second, a third, and a fourth board structure member, wherein a distance between the first and the third board structure members is longer than a distance between the second and the fourth board structure members. The differential trace pair system further includes a differential trace pair that includes a first differential trace extending between the first and the third board structure members and a second differential trace extending between the second and the fourth board structure members. The second differential trace having a serpentine structure that includes a first portion that continuously transitions away from the first differential trace and a second portion that is contiguous with the first portion, the second portion continuously transitions towards the first differential trace.

Abstract: A receiver includes signal lanes to receive associated data bit streams, and a control module. The signal lanes each include configurable equalization modules to provide a selectable compensation value to the associated data bit stream. The control module performs back channel adaptations on each data bit stream to achieve a target bit error rate for the associated signal lane, determines a most common set of compensation values from the performance of the back channel adaptations, determines whether the compensation value is within a predetermined boundary for that selectable compensation value, and provides an alert when a first compensation value of the most common set of compensation values is not within the predetermined boundary for the first compensation value.