Abstract: Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.

Abstract: Methods and structures for modulating an inner spacer profile include providing a fin having an epitaxial layer stack including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. In some embodiments, the method further includes removing the plurality of dummy layers to form a first gap between adjacent semiconductor channel layers of the plurality of semiconductor channel layers. Thereafter, in some examples, the method includes conformally depositing a dielectric layer to substantially fill the first gap between the adjacent semiconductor channel layers. In some cases, the method further includes etching exposed lateral surfaces of the dielectric layer to form an etched-back dielectric layer that defines substantially V-shaped recesses. In some embodiments, the method further includes forming a substantially V-shaped inner spacer within the substantially V-shaped recesses.

Abstract: An apparatus for chemically mechanically polishing includes an arm configured to move a conditioner module. The conditioner module is configured to contact a pad so as to change a degree of roughness of the pad. The pad is configured to contact and polish a semiconductor wafer. The arm has a first end and a second end opposite to the first end. The first end has an electromagnetic module. The conditioner module is detachably magnetically coupled to the arm by means of the electromagnetic module. The second end is coupled to a knob and configured to pivot at the knob. The arm moves the conditioner module through the pivoting of the second end at the knob. The conditioner module is disconnected from the arm when a magnetic polarity at the electromagnetic module is changed.

Abstract: The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a polishing head that is operable to perform a polishing process to a wafer. The apparatus includes a retaining ring that is rotatably coupled to the polishing head. The retaining ring is operable to secure the wafer to be polished. The apparatus includes a soft material component located within the retaining ring. The soft material component is softer than silicon. The soft material component is operable to grind a bevel region of the wafer during the polishing process. The apparatus includes a spray nozzle that is rotatably coupled to the polishing head. The spray nozzle is operable to dispense a cleaning solution to the bevel region of the wafer during the polishing process.

Abstract: An apparatus for chemically mechanically polishing includes an arm configured to move a conditioner module. The conditioner module is configured to contact a pad so as to change a degree of roughness of the pad. The pad is configured to contact and polish a semiconductor wafer. The arm has a first end and a second end opposite to the first end. The first end has an electromagnetic module. The conditioner module is detachably magnetically coupled to the arm by means of the electromagnetic module. The second end is coupled to a knob and configured to pivot at the knob. The arm moves the conditioner module through the pivoting of the second end at the knob. The conditioner module is disconnected from the arm when a magnetic polarity at the electromagnetic module is changed.

Abstract: A method of planarizing a wafer includes pressing the wafer against a planarization pad. The method further includes moving the planarization pad relative to the wafer. The method further includes conditioning the planarization pad using a pad conditioner. Conditioning the planarization pad includes moving the planarization pad relative to the pad conditioner. The pad conditioner includes abrasive particles having aligned tips a substantially constant distance from a surface of substrate of the pad conditioner.

Abstract: A method of forming a semiconductor package includes depositing a passivation layer overlying a semiconductor substrate, wherein the semiconductor substrate includes a scribe line region positioned between a first chip region and a second chip region. The method further includes forming a bump overlying the passivation layer on at least one of the first chip region or the second chip region, wherein the bump comprises a copper pillar and a cap layer. The method further includes forming a groove passing through the passivation layer on the scribe line region, wherein the groove extends into the semiconductor substrate to expose a stepped sidewall of the semiconductor substrate. The method further includes applying a molding compound layer to cover the passivation layer and a lower portion of the bump and fill the groove. The method further includes singulating along the scribe line region.

Abstract: A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units.

Abstract: System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.

Abstract: A method of forming a semiconductor package includes forming a passivation layer over a semiconductor substrate. The semiconductor substrate includes a first chip region, a second chip region and a scribe line region. The scribe line region is positioned between the first chip region and the second chip region. The method also includes forming a bump over the passivation layer on at least one of the first chip region and the second chip region. The method further includes removing a portion of the passivation layer to form a groove in the passivation layer on the scribe line region. The method additionally includes filling the groove with a molding compound layer. The molding compound layer is filled to a point that entirely fills the groove, covers the passivation layer, and covers a lower portion of the bump. The method also includes separating the first chip region from the second chip region along the scribe line region.

Abstract: A method of forming a semiconductor package includes depositing a passivation layer overlying a semiconductor substrate, wherein the semiconductor substrate includes a scribe line region positioned between a first chip region and a second chip region. The method further includes forming a bump overlying the passivation layer on at least one of the first chip region or the second chip region, wherein the bump comprises a copper pillar and a cap layer. The method further includes forming a groove passing through the passivation layer on the scribe line region, wherein the groove extends into the semiconductor substrate to expose a stepped sidewall of the semiconductor substrate. The method further includes applying a molding compound layer to cover the passivation layer and a lower portion of the bump and fill the groove. The method further includes singulating along the scribe line region.

Abstract: Methods and apparatus for detecting errors in real time in CMP processing. A method includes disposing a semiconductor wafer onto a wafer carrier in a tool for chemical mechanical polishing (“CMP”); positioning the wafer carrier so that a surface of the semiconductor wafer contacts a polishing pad mounted on a rotating platen; dispensing an abrasive slurry onto the rotating polishing pad while maintaining the surface of the semiconductor wafer in contact with the polishing pad to perform a CMP process on the semiconductor wafer; in real time, receiving signals from the CMP tool into a signal analyzer, the signals corresponding to vibration, acoustics, temperature, or pressure; and comparing the received signals from the CMP tool to expected received signals for normal processing by the CMP tool; outputting a result of the comparing. A CMP tool apparatus is disclosed.

Abstract: A semiconductor package includes a passivation layer overlying a semiconductor substrate, a pillar bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. A sidewall of the passivation layer is covered by the molding compound layer.

Abstract: A method of planarizing a wafer includes pressing the wafer against a planarization pad. The method further includes moving the planarization pad relative to the wafer. The method further includes conditioning the planarization pad using a pad conditioner. Conditioning the planarization pad includes moving the planarization pad relative to the pad conditioner. The pad conditioner includes abrasive particles having aligned tips a substantially constant distance from a surface of substrate of the pad conditioner.

Abstract: A semiconductor package includes a passivation layer overlying a semiconductor substrate, a bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. A sidewall of the passivation layer is covered by the molding compound layer.

Abstract: A manufacture includes a substrate, a reinforcement layer over the substrate, and abrasive particles over the substrate. The abrasive particles are partially buried in the reinforcement layer. Upper tips of the abrasive particles are substantially coplanar.

Abstract: A method of forming a semiconductor package includes forming a passivation layer over a semiconductor substrate. The semiconductor substrate includes a first chip region, a second chip region and a scribe line region. The scribe line region is positioned between the first chip region and the second chip region. The method also includes forming a bump over the passivation layer on at least one of the first chip region and the second chip region. The method further includes removing a portion of the passivation layer to form a groove in the passivation layer on the scribe line region. The method additionally includes filling the groove with a molding compound layer. The molding compound layer is filled to a point that entirely fills the groove, covers the passivation layer, and covers a lower portion of the bump. The method also includes separating the first chip region from the second chip region along the scribe line region.

Abstract: A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units.

Abstract: The present disclosure relates to a two-phase cleaning element that enhances polishing pad cleaning so as to prevent wafer scratches and contamination in chemical mechanical polishing (CMP) processes. In some embodiments, the two-phase pad cleaning element comprises a first cleaning element and a second cleaning element configured to successively operate upon a section of a CMP polishing pad. The first cleaning element comprises a megasonic cleaning jet configured to utilize cavitation energy to dislodge particles embedded in the CMP polishing pad without damaging the surface of the polishing pad. The second cleaning element is configured to apply a high pressure mist, comprising two fluids, to remove by-products from the CMP polishing pad. By using megasonic cleaning to dislodge embedded particles a two-fluid mist to flush away by-products (e.g., including the dislodged embedded particles), the two-phase pad cleaning element enhances polishing pad cleaning.

Abstract: A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units.