Abstract: An apparatus for chemically mechanically polishing includes an arm configured to move a conditioner module. The conditioner module is configured to contact a pad so as to change a degree of roughness of the pad. The pad is configured to contact and polish a semiconductor wafer. The arm has a first end and a second end opposite to the first end. The first end has an electromagnetic module. The conditioner module is detachably magnetically coupled to the arm by means of the electromagnetic module. The second end is coupled to a knob and configured to pivot at the knob. The arm moves the conditioner module through the pivoting of the second end at the knob. The conditioner module is disconnected from the arm when a magnetic polarity at the electromagnetic module is changed.

Abstract: System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.

Abstract: System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate.

Abstract: A semiconductor package includes a passivation layer overlying a semiconductor substrate, a pillar bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. A sidewall of the passivation layer is covered by the molding compound layer.

Abstract: An integrated circuit structure includes a first die including TSVs; a second die over and bonded to the first die, with the first die having a surface facing the second die; and a molding compound including a portion over the first die and the second die. The molding compound contacts the surface of the second die. Further, the molding compound includes a portion extending below the surface of the second die.

Abstract: A method of forming an integrated circuit structure is provided. In an embodiment, the method includes bonding top dies onto a bottom wafer and then molding a first molding material onto and in between the top dies and the bottom wafer. The bottom wafer, the top dies, and the first molding material are sawed to form molding units. Each of the molding units includes one of the top dies and a bottom die sawed from the bottom wafer. The molding units are bonded onto a package substrate and a second molding material is molding onto the one of the molding units and the package substrate. Thereafter, the package substrate and the second molding material are sawed to form package-molded units.

Abstract: An integrated circuit structure includes a bottom die; a top die bonded to the bottom die with the top die having a size smaller than the bottom die; and a molding compound over the bottom die and the top die. The molding compound contacts edges of the top die. The edges of the bottom die are vertically aligned to respective edges of the molding compound.

Abstract: A semiconductor package includes a passivation layer overlying a semiconductor substrate, a bump overlying the passivation layer, and a molding compound layer overlying the passivation layer and covering a lower portion of the bump. A sidewall of the passivation layer is covered by the molding compound layer.

Abstract: A manufacture includes a substrate, a reinforcement layer over the substrate, and abrasive particles over the substrate. The abrasive particles are partially buried in the reinforcement layer. Upper tips of the abrasive particles are substantially coplanar.

Abstract: Some embodiments relate to a chemical mechanical polishing (CMP) system. The CMP system includes a polishing pad having a polishing surface, and a wafer carrier to retain a wafer proximate to the polishing surface during polishing. A motor assembly rotates the polishing pad and concurrently rotates the wafer during polishing of the wafer. A conditioning disk has a conditioning surface that is in frictional engagement with the polishing surface during polishing. A torque measurement element measures a torque exerted by the motor assembly during polishing. A condition surface analyzer determines a surface condition of the conditioning surface or the polishing surface based on the measured torque. Other systems and methods are also disclosed.

Abstract: The present disclosure relates to a two-phase cleaning element that enhances polishing pad cleaning so as to prevent wafer scratches and contamination in chemical mechanical polishing (CMP) processes. In some embodiments, the two-phase pad cleaning element comprises a first cleaning element and a second cleaning element configured to successively operate upon a section of a CMP polishing pad. The first cleaning element comprises a megasonic cleaning jet configured to utilize cavitation energy to dislodge particles embedded in the CMP polishing pad without damaging the surface of the polishing pad. The second cleaning element is configured to apply a high pressure mist, comprising two fluids, to remove by-products from the CMP polishing pad. By using megasonic cleaning to dislodge embedded particles a two-fluid mist to flush away by-products (e.g., including the dislodged embedded particles), the two-phase pad cleaning element enhances polishing pad cleaning.

Abstract: To provide improved planarization, techniques in accordance with this disclosure include a CMP station that includes a plurality of concentric temperature control elements arranged over a number of concentric to-be-polished wafer surfaces. During polishing, a wafer surface planarity sensor monitors relative heights of the concentric to-be-polished wafer surfaces, and adjusts the temperatures of the concentric temperature control elements to provide an extremely well planarized wafer surface. Other systems and methods are also disclosed.

Abstract: A method of forming a stacked die structure is disclosed. A plurality of dies are respectively bonded to a plurality of semiconductor chips on a first surface of a wafer. An encapsulation structure is formed over the plurality of dies and the first surface of the wafer. The encapsulation structure covers a central portion of the first surface of the wafer and leaves an edge portion of the wafer exposed. A protective material is formed over the first surface of the edge portion of the wafer.

Abstract: The present disclosure provides an apparatus for fabricating a semiconductor device. The apparatus includes a polishing head that is operable to perform a polishing process to a wafer. The apparatus includes a retaining ring that is rotatably coupled to the polishing head. The retaining ring is operable to secure the wafer to be polished. The apparatus includes a soft material component located within the retaining ring. The soft material component is softer than silicon. The soft material component is operable to grind a bevel region of the wafer during the polishing process. The apparatus includes a spray nozzle that is rotatably coupled to the polishing head. The spray nozzle is operable to dispense a cleaning solution to the bevel region of the wafer during the polishing process.

Abstract: Methods and apparatus for detecting errors in real time in CMP processing. A method includes disposing a semiconductor wafer onto a wafer carrier in a tool for chemical mechanical polishing (“CMP”); positioning the wafer carrier so that a surface of the semiconductor wafer contacts a polishing pad mounted on a rotating platen; dispensing an abrasive slurry onto the rotating polishing pad while maintaining the surface of the semiconductor wafer in contact with the polishing pad to perform a CMP process on the semiconductor wafer; in real time, receiving signals from the CMP tool into a signal analyzer, the signals corresponding to vibration, acoustics, temperature, or pressure; and comparing the received signals from the CMP tool to expected received signals for normal processing by the CMP tool; outputting a result of the comparing. A CMP tool apparatus is disclosed.

Abstract: A method provides a first substrate with a conductive pad and disposes layers of Cu, TaN, and AlCu, respectively, forming a conductive stack on the conductive pad. The AlCu layer of the first substrate is bonded to a through substrate via (TSV) structure of a second substrate, wherein a conductive path is formed from the conductive pad of the first substrate to the TSV structure of the second substrate.

Abstract: An integrated circuit structure includes a first die including TSVs; a second die over and bonded to the first die, with the first die having a surface facing the second die; and a molding compound including a portion over the first die and the second die. The molding compound contacts the surface of the second die. Further, the molding compound includes a portion extending below the surface of the second die.

Abstract: A method provides a first substrate with a conductive pad and disposes layers of Cu, TaN, and AlCu, respectively, forming a conductive stack on the conductive pad. The AlCu layer of the first substrate is bonded to a through substrate via (TSV) structure of a second substrate, wherein a conductive path is formed from the conductive pad of the first substrate to the TSV structure of the second substrate.

Abstract: An integrated circuit structure includes a bottom die; a top die bonded to the bottom die with the top die having a size smaller than the bottom die; and a molding compound over the bottom die and the top die. The molding compound contacts edges of the top die. The edges of the bottom die are vertically aligned to respective edges of the molding compound.

Abstract: A method provides a first substrate with a conductive pad and disposes layers of Cu, TaN, and AlCu, respectively, forming a conductive stack on the conductive pad. The AlCu layer of the first substrate is bonded to a through substrate via (TSV) structure of a second substrate, wherein a conductive path is formed from the conductive pad of the first substrate to the TSV structure of the second substrate.