Abstract: Embodiments of the invention include a transistor comprising a gate region and an epitaxial region, the transistor comprising a frontside opposite a backside.

Abstract: A field effect transistor (FET) cell structure of an integrated circuit (IC) is provided. The FET cell structure includes first and second adjacent cells. Each of the first and second adjacent cells spans a first layer and a second layer. The second layer is vertically stacked on the first layer. The first cell includes n-doped FETs (NFETs) on one of the first and second layers and p-doped FETs (PFETs) on another of the first and second layers. The second cell includes at least one of a number of NFETs on the one of the first and second layers differing from a number of the NFETs in the first cell and a number of PFETs on the another of the first and second layers differing from a number of the PFETs in the first cell.

Abstract: A semiconductor apparatus includes a substrate; a first conductive feature disposed on the substrate, the first conductive feature comprising a conductive material; a second conductive feature disposed on the substrate, the second conductive feature comprising the conductive material; a dielectric material at least partially surrounding the first conductive feature and the second conductive feature; and an interconnect between the first conductive feature and the second conductive feature, the interconnect comprising the conductive material integral with the first conductive feature and the second conductive feature and extending through the dielectric material and below the first conductive feature and the second conductive feature.

Abstract: A semiconductor structure includes a first stacked device structure. The first stacked device structure includes a first field-effect transistor disposed on a substrate having a front side and a back side. The first field-effect transistor has a first source/drain region. The first stacked device structure further includes a second field-effect transistor vertically stacked above the first field-effect transistor. The second field-effect transistor has a second source/drain region. The first stacked device structure further includes a first front side source/drain contact disposed on the first source/drain region and a first back side source/drain contact disposed on the second source/drain region. The first stacked device structure further includes a first isolation pillar structure located within the first field-effect transistor, the second field-effect transistor, the first front side source/drain contact and the first back side source/drain contact.

Abstract: A semiconductor device includes a first vertical field-effect transistor comprising a first set of vertical fins and a second set of vertical fins separated by a first isolation pillar structure. The semiconductor device further includes a second vertical field-effect transistor adjacent to the first vertical field-effect transistor, the second vertical field-effect transistor comprising a first set of vertical fins and a second set of vertical fins separated by a second isolation pillar structure.

Abstract: An integrated circuit (IC) assembly method is provided. The method includes fabricating a first wafer including a first device with a back end of line (BEOL) and first terminals of first and second types at the BEOL and fabricating a second wafer including a second device for back side power delivery network (BSPDN) processing, second terminals of the first type, first vias and second vias. The first and second wafers are bonded at the BEOL to connect the second terminals of the first type to a subset of the first terminals of the first type, the first vias to remaining first terminals of the first type, and the second vias to the first terminals of the second type. A BSPDN is built onto a backside of the second wafer to include first and second BSPDN terminals connected to the first and second vias, respectively.

Abstract: A semiconductor structure is provided that includes a first pair of stacked devices located in a first active device region and a second pair of stacked devices located in a second active device region. Each stacked device of the pair of stacked devices includes a second field effect transistor (FET) stacked over a first FET, and within each active device region the pair of stacked devices is separated by an inter-device dielectric pillar. A local interconnect structure is located in a non-active device region that is positioned between the first and second active device regions. The local interconnect structure can be connected to a back side power rail and a source/drain region of one of the second FETs, or connected to a front side signal line and a source/drain region of one of the first FETs.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a first trench partially through a first substrate from a first side of the first substrate. The method also includes widening a bottom portion of the first trench to form a lateral footing area of the first trench. The method includes forming a first metallization in the first trench; forming a second trench through a second substrate from a second side of the second substrate to expose at least a portion of first metallization in an area corresponding to the lateral footing area of the first trench, the second side being opposite to the first side. The method also includes forming a second metallization in the second trench in contact with the first metallization.

Abstract: An approach forming semiconductor structure composed of a first plurality of vertical transport field-effect transistors in a lower semiconductor layer and a second plurality of vertical transport field-effect transistors in an upper semiconductor layer. The second plurality of vertical transport field-effect transistors is horizontally offset from the first plurality of vertical transport field-effect transistors by a horizontal distance that is one-half of a contacted gate pitch between adjacent vertical transport field-effect transistors in the same semiconductor layer.

Abstract: A backside power distribution network is provided having an integrated signal line with a backside connection to a transistor gate. In one aspect, a semiconductor device includes: NFETs and PFETs adjacent to one another on a frontside of a wafer; power rails, connected to source/drain regions of the NFETs and PFETs, present on a backside of the wafer in a space between adjacent NFETs and in a space between adjacent PFETs; and a signal line, connected to a gate of the NFETs and PFETs, present on the backside of the wafer in a space between an adjacent NFET and PFET. The NFETs and PFETs can each include a stack of active layers, and gates surrounding at least a portion of each of the active layers in a gate-all-around configuration. A method of fabricating the present semiconductor devices is provided.

Abstract: A microelectronic structure including a static random-access memory (SRAM) device that includes a plurality of stacked transistors. Each of the plurality of stacked transistors that includes a bottom transistor and an upper transistor, where the upper transistor is not in vertical alignment with the bottom transistor.

Abstract: A back side contact structure is provided that directly connects a first electrode of a MRAM, which is present in a back side of a wafer, to a source/drain structure of a transistor. The back side contact is self-aligned to the source/drain structure of the transistor as well as to the first electrode of the MRAM. The close proximity between the MRAM and the source/drain structure increases the speed of the device. MRAM yield is not compromised since no re-sputtering of back side contact metal onto the MRAM occurs.

Abstract: A semiconductor device containing a self-aligned contact rail is provided. The self-aligned contact rail can have a reduced critical dimension, CD. The self-aligned contact rail can be obtained utilizing a sacrificial semiconductor fin as a placeholder structure for the contact rail. The used of the sacrificial semiconductor fin enables reduced, and more controllable, CDs.

Abstract: Interconnect designs with reduced via resistance are provided. In one aspect, an interconnect structure includes: at least a first metal line and a second metal line; and a conductive via in between the first metal line and the second metal line, wherein the conductive via has elongated dimensions along a major axis of the first metal line and along a major axis of the second metal line. Dielectric caps can be present on the first metal lines, and below and above the second metal lines. A method of forming the present interconnect structure is also provided.

Abstract: A method of forming a top via is provided. The method includes forming a sacrificial trench layer and conductive trench plug in an interlayer dielectric (ILD) layer on a conductive line. The method further includes forming a cover layer on the ILD layer, sacrificial trench layer, and conductive trench plug, and forming a sacrificial channel layer and a conductive channel plug on the conductive trench plug. The method further includes removing the cover layer and the ILD layer to expose the sacrificial trench layer and the sacrificial channel layer. The method further includes removing the sacrificial trench layer and the sacrificial channel layer, and forming a barrier layer on the conductive channel plug and conductive trench plug.

Abstract: A microelectronic structure comprises a first interconnect line at a first interconnect level, a second interconnect line at a second interconnect level, and at least one via connecting the first interconnect line at the first interconnect level to the second interconnect line at the second interconnect level. The at least one via comprises a vertical section and at least one horizontal section, the at least one horizontal section being in contact with at least a portion of one of a top surface of the first interconnect line and a bottom surface of the second interconnect line.

Abstract: An approach providing a semiconductor wiring structure with a self-aligned top via on a first metal line and under a second metal line. The semiconductor wiring structure includes a plurality of first metal lines in a bottom portion of a first dielectric material. The semiconductor wiring structure includes a top via in a top portion of the first dielectric material, where the top via is over a first metal line of the plurality of first metal lines. The semiconductor wiring structure includes a second dielectric material above each of the plurality of first metal lines except the first metal line of the plurality of first metal lines. Furthermore, the semiconductor wiring structure includes a second metal line above the top via, wherein the second metal line is in a third dielectric material and a hardmask layer that is under the third dielectric material.

Abstract: A semiconductor device is provided that includes at least one stacked FET device including two top transistors stacked over a single bottom transistor. The at least one stacked FET includes a full gate cut structure that is used to separate different device areas from each other, a top gate cut structure that used to separate the two top transistors, and a bottom gate cut structure that is used to provide the single bottom transistor. The at least one FET device can be used to provide a SRAM containing six transistors.

Abstract: Provided is a semiconductor device. The semiconductor device comprises a plurality of logic devices. The logic devices have frontside wiring. The semiconductor device further comprises a backside power delivery network (BSPDN). The semiconductor device further comprises a connection between the BSPDN and the bottom of a source/drain epitaxy of a logic device. The connection is self-aligned on at least two sides.

Abstract: A plurality of transistor components, a system, and a method of forming a vertically stacked transistor structure within a wafer. The plurality of transistor components may include a first bottom transistor, where the first bottom transistor includes a channel, a gate, a source, and a drain. The plurality of transistor components may also include a first contact on top of the first bottom transistor, where the first contact is proximately connected to the first bottom transistor. The plurality of transistor components may also include a first set of stacked transistors, where the first set of stacked transistors includes a second top transistor on top of a second bottom transistor.