Patents by Inventor Brent Anderson

Brent Anderson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SUBTRACTIVE SOURCE DRAIN CONTACT FOR STACKED DEVICES
    Publication number: 20230420502
    Abstract: A field effect transistor (“FET”) stack, including a lower FET, and an upper FET, a first contact to a lower source drain of the lower FET, a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain, a first overlap region between the first silicide and the first contact is less than a second overlap region between the first silicide and the first source drain. The first contact has a reverse tapper metal stud profile. Forming a first contact to a lower source drain of a lower FET of an FET stack, forming a first silicide between the first contact and the lower source drain, the first contact is adjacent to a vertical side surface of the lower source drain.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Inventors: Heng Wu, Junli Wang, Ruilong Xie, Albert M. Young, Albert M. Chu, Brent A. Anderson, Ravikumar Ramachandran
  • SEMICONDUCTOR DEVICE WITH POWER VIA
    Publication number: 20230420359
    Abstract: A semiconductor device is provided. The semiconductor device includes a field effect transistor (FET) including first and second source/drain (S/D) epitaxial regions. The semiconductor device also includes a gate cut region at cell boundaries between the first and second S/D epitaxial regions, a dielectric liner and a dielectric core formed in the gate cut region, and a backside power rail (BPR) and a backside power distribution network (BSPDN). The semiconductor device also includes a power via passing through the dielectric core and connecting to the BPR and BSPDN, first metal contacts formed in contact with the first and second S/D epitaxial regions, and a via to backside power rail (VBPR) contact. The dielectric liner separates the power via from the first S/D epitaxial region.
    Type: Application
    Filed: June 22, 2022
    Publication date: December 28, 2023
    Inventors: Ruilong Xie, Junli Wang, Kisik Choi, Julien Frougier, Reinaldo Vega, Lawrence A. Clevenger, Albert M. Chu, Brent A. Anderson
  • STACKED FIELD EFFECT TRANSISTOR CELL WITH CROSS-COUPLING
    Publication number: 20230420371
    Abstract: Embodiments are disclosed for a complementary metal oxide semiconductor (CMOS) device. The CMOS device includes a hybrid cross-couple contact. The hybrid cross-couple contact includes a frontside contact to a gate of the CMOS device. The frontside contact is disposed on a frontside of the CMOS device. The hybrid cross-couple contact includes a source contact to a source of the CMOS device. The source contact is disposed on a backside of the CMOS device. The hybrid cross-couple contact includes a drain contact to a drain of the CMOS device. The drain contact is disposed on a backside of the CMOS device.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Carl Radens, Ruilong Xie, Albert M. Chu, Brent A. Anderson
  • Vertical FET with contact to gate above active fin
    Patent number: 11855191
    Abstract: An apparatus includes a fin, a gate, and a gate contact. A portion of the fin is disposed in a first layer. The gate is disposed in the first layer and adjacent to the fin. The gate contact is disposed on the gate and in a second layer, wherein the second layer is disposed on the first layer such that the gate contact is above the fin.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: December 26, 2023
    Assignee: International Business Machines Corporation
    Inventors: Brent Anderson, Junli Wang, Indira Seshadri, Chen Zhang, Ruilong Xie, Joshua M. Rubin, Hemanth Jagannathan
  • METHOD AND STRUCTURE OF FORMING CONTACTS AND GATES FOR STAGGERED FET
    Publication number: 20230411386
    Abstract: A microelectronic structure including a plurality of lower transistors and a plurality of upper transistors, where channels of the upper transistors are staggered from channels of the lower transistors. A lower dielectric pillar located beneath an upper transistor, where the dielectric pillar separates bottom transistors.
    Type: Application
    Filed: June 20, 2022
    Publication date: December 21, 2023
    Inventors: Ruilong Xie, Albert M. Chu, Junli Wang, Brent A. Anderson, Anthony I. Chou, Dechao Guo
  • HEAT PIPE FOR VERTICALLY STACKED FIELD EFFECT TRANSISTORS
    Publication number: 20230411241
    Abstract: A heat pipe is provided as an electrically inactive structure to dissipate heat that is generated by vertically stacked field effect transistors (FETs). The heat pipe is present in an electrically inactive device area which is located adjacent to an electrically active device area that includes the vertically stacked FETs.
    Type: Application
    Filed: June 15, 2022
    Publication date: December 21, 2023
    Inventors: Terence Hook, Brent A. Anderson, Anthony I. Chou
  • METHOD AND STRUCTURE OF FORMING INDEPENDENT CONTACT FOR STAGGERED CFET
    Publication number: 20230411358
    Abstract: A microelectronic structure including a plurality of lower transistors and a plurality of upper transistor, where each of the plurality of lower transistors and the plurality of upper transistors includes a plurality of channel. Where an upper center vertical axis of each of the plurality of upper transistors is staggered from a lower center vertical axis of each of the lower transistors. A lower gate cut is located between each of the plurality of lower transistors. A first upper gate cut located adjacent to a first upper transistor of the plurality of upper transistors, where the first upper gate cut is in direct contact with a plurality of first channels of the first upper transistor.
    Type: Application
    Filed: June 20, 2022
    Publication date: December 21, 2023
    Inventors: Ruilong Xie, Albert M. Chu, Albert M. Young, Brent A. Anderson, Junli Wang, Ravikumar Ramachandran
  • STACKED FIELD EFFECT TRANSISTOR
    Publication number: 20230402519
    Abstract: A semiconductor device is provided. The semiconductor device includes a bottom field effect transistor (FET) including a bottom source-drain epitaxial layer formed on sides of the bottom FET; a top FET stacked over the bottom FET; a back-end-of-line (BEOL) layer formed on the top FET; a bottom gate contact formed in contact with the bottom FET and having an extending portion of the bottom gate contact that extends laterally over the bottom source-drain epitaxial layer; and a top gate contact formed in contact with the extending portion of the bottom gate contact and electrically connecting the bottom gate contact to the BEOL layer.
    Type: Application
    Filed: June 10, 2022
    Publication date: December 14, 2023
    Inventors: Brent A. Anderson, Ruilong Xie, Albert M. Young, Albert M. Chu
  • Advanced metal interconnects with a replacement metal
    Patent number: 11842961
    Abstract: An approach to provide a semiconductor structure using different two metal materials for interconnects in the middle of the line and the back end of the line metal layers of a semiconductor chip. The semiconductor structure includes the first metal material connecting both horizontally and vertically with the second metal material and the second metal material connecting both horizontally and vertically with the first metal material where the second metal material is more resistant to electromigration than the first metal material.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: December 12, 2023
    Assignee: International Business Machines Corporation
    Inventors: Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Brent Anderson
  • VTFET WITH BURIED POWER RAILS
    Publication number: 20230387295
    Abstract: A semiconductor device is provided. The semiconductor device includes a buried power rail, a buried oxide (BOX) layer formed on the buried power rail, a plurality of channel fins formed on the BOX layer, a bottom epitaxial layer formed on the BOX layer and between the channel fins such that the BOX layer is between the buried power rail and the bottom epitaxial layer, a gate stack formed over the bottom epitaxial layer and contacting the channel fins, the gate stack including a work function metal (WFM) layer and a high-x layer, and a top epitaxial layer formed on the gate stack. In the semiconductor device, between two adjacent ones of the channel fins the BOX layer has an opening so that the bottom epitaxial layer is electrically connected to the buried power rail.
    Type: Application
    Filed: August 10, 2023
    Publication date: November 30, 2023
    Inventors: Chen Zhang, Ruilong Xie, Heng Wu, Junli Wang, Brent A. Anderson
  • INTERCONNECT THROUGH GATE CUT FOR STACKED FET DEVICE
    Publication number: 20230387007
    Abstract: A microelectronic structure including a stacked device region, where stacked device region is comprised of a plurality of top devices and a plurality of bottom devices. Each of the plurality of top devices includes at least one top source/drain. Each of the plurality of bottom devices includes at least one bottom source/drain. A gate cut region located adjacent to the stacked region and an interconnect located in the gate cut region. The interconnect is connected to at least two different devices located in the stacked device region.
    Type: Application
    Filed: May 25, 2022
    Publication date: November 30, 2023
    Inventors: Ruilong Xie, Albert M. Young, Brent A. Anderson, Julien Frougier, Kangguo Cheng, CHANRO PARK
  • Buried contact through fin-to-fin space for vertical transport field effect transistor
    Patent number: 11830774
    Abstract: Embodiments of the present invention are directed to fabrication methods and resulting structures that provide buried contacts in the fin-to-fin space of vertical transport field effect transistors (VFETs) that connect the bottom S/D of the transistors to a buried power rail. In a non-limiting embodiment of the invention, a buried power rail is encapsulated in a buried oxide layer of a first wafer. First and second semiconductor fins are formed on a second wafer. The first wafer to the second wafer and a surface of the buried power rail in a fin-to-fin space is exposed. A buried via is formed on the exposed surface of the buried power rail. The buried via electrically couples the buried power rail to a bottom source or drain region of the first semiconductor fin.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: November 28, 2023
    Assignee: International Business Machines Corporation
    Inventors: Junli Wang, Brent Anderson
  • METHOD AND STRUCTURE FOR A LOGIC DEVICE AND ANOTHER DEVICE
    Publication number: 20230378258
    Abstract: A method including forming an oxide layer on a first substrate and forming a second substrate on the oxide layer. Doping a first section of the second substrate while not doping a second section of the second substrate. Forming a first nano device on the second section of the second substrate and forming a second nano device on first section of the second substrate. Flipping the first substrate over to allow for backside processing of the substrate and forming at least one backside contact connected to the first nano device while backside contacts are not formed or connected to the second nano device.
    Type: Application
    Filed: May 17, 2022
    Publication date: November 23, 2023
    Inventors: Ruilong Xie, Anthony I. Chou, Brent A. Anderson, John Christopher Arnold, Junli Wang, Kai Zhao, Terence Hook, Julien Frougier, Xuefeng Liu
  • Top via with next level line selective growth
    Patent number: 11823998
    Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: November 21, 2023
    Assignee: International Business Machines Corporation
    Inventors: Brent Anderson, Lawrence A. Clevenger, Christopher J. Penny, Nicholas Anthony Lanzillo, Kisik Choi, Robert Robison
  • LOCAL INTERCONNECT FOR CROSS COUPLING
    Publication number: 20230360971
    Abstract: Embodiments of present invention provide a transistor structure. The transistor structure includes a first and a second transistor in a first transistor layer; a first and a second transistor in a second transistor layer, respectively, above the first and the second transistor in the first transistor layer; a metal routing layer between the first transistor layer and the second transistor layer; a first local interconnect connecting the first transistor of the first transistor layer to the metal routing layer; and a second local interconnect connecting the metal routing layer to the second transistor of the second transistor layer. A method of manufacturing the transistor structure is also provided.
    Type: Application
    Filed: May 9, 2022
    Publication date: November 9, 2023
    Inventors: Heng Wu, Ruilong Xie, Albert M. Chu, Albert M. Young, Junli Wang, Brent A. Anderson
  • Top via cut fill process for line extension reduction
    Patent number: 11804406
    Abstract: An interconnect structure including a top via with a minimum line end extension comprises a cut filled with an etch stop material. The interconnect structure further comprises a line formed adjacent to the etch stop material. The interconnect structure further comprises a top via formed on the line adjacent to the etch stop material, wherein the top via utilizes the etch stop material to achieve minimum line extension.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: October 31, 2023
    Assignee: International Business Machines Corporation
    Inventors: Christopher J. Penny, Brent Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Robert Robison
  • CROSS-COUPLING CONNECTIONS FOR STACKED FIELD EFFECT TRANSISTORS
    Publication number: 20230343821
    Abstract: A semiconductor device including a first pair of stacked transistors comprising a first upper transistor and a first lower transistor, a third transistor disposed adjacent to the first lower transistor, the third transistor comprising a gate portion extending from the third transistor gate toward the first pair of stacked transistors, a cross-connection disposed in contact with the gate portion and extending upward, and a gate contact disposed in contact with the cross-connection and a top surface of the first upper transistor.
    Type: Application
    Filed: April 25, 2022
    Publication date: October 26, 2023
    Inventors: Ruilong Xie, Heng Wu, Albert M. Young, Albert M Chu, Junli Wang, Brent A Anderson
  • STACKED FIELD-EFFECT TRANSISTORS HAVING LATCH CROSS-COUPLING CONNECTIONS
    Publication number: 20230335585
    Abstract: A semiconductor device including a first pair of stacked transistors having a first upper transistor and a first lower transistor, a second pair of stacked transistors comprising a second upper transistor and a second lower transistor, and a first cross-connection between the first upper transistor and the second lower transistor.
    Type: Application
    Filed: April 17, 2022
    Publication date: October 19, 2023
    Inventors: Ruilong Xie, Albert M. Chu, Albert M. Young, Anthony I. Chou, Junli Wang, Brent A. Anderson
  • Conductive lines with subtractive cuts
    Patent number: 11791258
    Abstract: Integrated chips include a dielectric layer that includes at least one trench and at least one plug region. A line is formed in the dielectric layer in the at least one trench and terminates at the plug region. A dielectric plug is formed in the plug region.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: October 17, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent Anderson, Lawrence A. Clevenger, Kisik Choi, Nicholas Anthony Lanzillo, Christopher J. Penny, Robert Robison
  • POWER DISTRIBUTION NETWORKS FOR SEMICONDUCTOR CHIP
    Publication number: 20230326854
    Abstract: Embodiments of present invention provide a semiconductor chip. The semiconductor chip includes a device layer having a first and a second circuit region; a frontside distribution network (FSDN) above the device layer and powering the first circuit region; and a backside distribution network (BSDN) below the device layer and powering the second circuit region, wherein the BSDN is electrically connected to the FSDN through the device layer and the FSDN is electrically connected to the first circuit region through one or more frontside metal layers, and wherein the BSDN is electrically connected to transistors of the second circuit region through the device layer.
    Type: Application
    Filed: April 8, 2022
    Publication date: October 12, 2023
    Inventors: Albert M. Chu, Brent A. Anderson, Junli Wang, John W. Golz, Nicholas Anthony Lanzillo, Lawrence A. Clevenger