Abstract: A magnetic laminating structure and process for preventing substrate bowing include a first magnetic layer, at least one additional magnetic layer, and a dielectric spacer disposed between the first and at least one additional magnetic layers. The magnetic layers are characterized by defined tensile strength. To balance the tensile strength of the magnetic layer, the dielectric layer is selected to provide compressive strength so as to counteract the tendency of the wafer to bow as a consequence of the tensile strength imparted by the magnetic layer(s).

Abstract: A semiconductor structure and fabrication method of forming a semiconductor structure. The structure is a MRAM element having a first conductive electrode embedded in a first interconnect dielectric material layer upon which a multi-layered magnetic tunnel junction (MTJ) memory element is formed in a magnetoresistive random access memory (MRAM) device area. The first conductive electrode includes a first end having a top surface of a first surface area and a second end having a bottom surface of a second surface area, the first surface area being smaller than the second surface area. The second end of the bottom electrode includes a barrier liner material including a metal fill material, and the first end of the bottom electrode is a pillar structure formed as a result of an etchback process in which the metal barrier liner is recessed relative to the metal fill material.

Abstract: Semiconductor devices and methods relating to the semiconductor devices are provided. A semiconductor device includes a resonant clock circuit. The semiconductor device further includes an inductor. The semiconductor device also includes a magnetic layer formed of a magnetic material disposed in between a portion of the resonant clock circuit and the inductor. Clock signals of the resonant clock circuit are utilized by the magnetic layer.

Abstract: A bottom electrode structure for MRAM or MTJ-based memory cells comprises a taper so that the bottom CD is smaller than the top CD. A process of making a bottom electrode contact structure comprises etching a dielectric layer using a plasma chemistry with an increased degree of polymerization. We obtain a product made by this process.

Abstract: A magnetic tunnel junction (MTJ) containing device and methods of constructing the MTJ containing device are described. In an example, the MTJ containing device may be a memory element including a bottom electrode structure, a MTJ pillar, and a top electrode structure located on the MTJ pillar. The MTJ pillar has a non-circular lateral cross section, where the MTJ pillar has a bottommost portion forming an interface with an uppermost portion of the bottom electrode structure. The MTJ pillar has a lateral perimeter-to-area ratio that defines a breakdown voltage of the MTJ pillar.

Abstract: A memory element and methods of constructing the memory element are described. The memory element may include a bottom electrode structure having an uppermost portion of a first dimension. The memory element may further include a MTJ pillar having a bottommost portion forming an interface with the uppermost portion of the bottom electrode structure. The bottommost portion of the MTJ pillar may have a second dimension that is less than the first dimension. The memory element may further include oxidized metal particles located on an outermost sidewall of the MTJ pillar. The memory element may further include a top electrode structure located in the MTJ pillar.

Abstract: A magnetic tunnel junction (MTJ) containing device and methods of constructing the MTJ containing device are described. In an example, the MTJ containing device may be a memory element including a bottom electrode structure, a MTJ pillar, and a top electrode structure located on the MTJ pillar. The MTJ pillar has a non-circular lateral cross section, where the MTJ pillar has a bottommost portion forming an interface with an uppermost portion of the bottom electrode structure. The MTJ pillar has a lateral perimeter-to-area ratio that defines a breakdown voltage of the MTJ pillar.

Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.

Abstract: Back end of line (BEOL) metallization structures and methods generally includes forming a landing pad on an interconnect structure. A multilayer structure including layers of metals and at least one insulating layer are provided on the structure and completely cover the landing pad. The landing pad is a metal-filled via and has a width dimension that is smaller than the multilayer structure, or the multilayer structure and the underlying metal conductor in the interconnect structure. The landing pad metal-filled via can have a width dimension that is sub-lithographic.

Abstract: A semiconductor structure and fabrication method of forming a semiconductor structure. The method first provides an electrically conductive structure embedded in an interconnect dielectric material layer of a magnetoresistive random access memory device. A conductive landing pad is located on a surface of the electrically conductive structure. A multilayered magnetic tunnel junction (MTJ) structure and an MTJ cap layer is formed on the landing pad. Then there is formed a first conductive layer on top the MTJ cap layer and a second conductive metal layer formed on top the first conductive layer. A pillar mask structure is then patterned and formed on the second conductive layer. The resulting structure is subject to lithographic patterning and etching to form a patterned bilayer metal hardmask pillar structure on top the MTJ cap layer. Subsequent etch processing forms an MTJ stack having sidewalls aligned to the patterned bilayer metal hardmask pillar.

Abstract: A memory system in an integrated circuit and a method of operation. The system includes multiple magnetic tunnel junction (MTJ) structures, each MTJ structure storing a logic value according to a resistive state. A selection switch device associated with a respective MTJ structure is activated to select one of the multiple MTJ structures at a time. An output circuit is configured to sense the resistive state of a selected MTJ structure, the output circuit having a selectable input reference resistance value according to a selected first reference resistance or a second reference resistance value, and outputting a first logic value of the selected MTJ structure responsive to a resistive state of the MTJ structure and a selected first resistance reference value, or alternately outputting a second logic value of the selected MTJ structure responsive to the resistive state of the MTJ structure and a selected second resistance reference value.

Abstract: Embodiments of the present invention are directed to a method for fabricating a magnetoresistive random access memory (MRAM) device. A non-limiting example of the method includes depositing a dielectric layer on a contact arranged on a substrate including a magnetic tunnel junction (MTJ) pillar. The method includes reducing a width of the MTJ pillar. The method further includes depositing an encapsulation layer on the dielectric layer and the MTJ pillar.

Abstract: Embodiments of the present invention are directed to a semiconductor device. A non-limiting example of the semiconductor device includes a semiconductor substrate. The semiconductor device also includes a plurality of metal nanopillars formed on the substrate. The semiconductor device also includes an amperometric sensor associated with one of the plurality of nanopillars, wherein the amperometric sensor is selective to an enzyme-active neurotransmitter. The semiconductor device also includes a resistivity sensor associated with a pair of nanopillars, wherein the resistivity sensor is selective to an analyte.

Abstract: A method of forming a magnetic tunnel junction (MTJ) containing device is provided in which a patterned sacrificial material is present atop a MTJ pillar that is located on a bottom electrode. A passivation material liner and a dielectric material portion laterally surround the MTJ pillar and the patterned sacrificial material. The patterned sacrificial material is removed from above the MTJ pillar and replaced with a top electrode. A seam is present in the top electrode. The method mitigates the possibility of depositing resputtered conductive metal particles on a sidewall of the MTJ pillar. Thus, improved device performance, in terms of a reduction in failure mode, can be obtained.

Abstract: A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.

Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.

Abstract: A magnetic tunnel junction (MTJ) containing device is provided in which a bottom electrode having a small CD is formed and is located laterally adjacent to diamond like carbon (DLC). DLC replaces a material stack of, from bottom to top, a silicon nitride layer and an organic planarization layer (OPL) which is typically used in providing a conductive structure having a reduced CD. DLC provides a higher etch resistance to IBE than silicon nitride, but DLC can be patterned using conventional etchants. The use of DLC thus reduces the number of processing steps for providing a reduced CD bottom electrode, and also provides a more robust solution to the issue of punch through to an underlying conductive material layer.

Abstract: A magnetic tunnel junction (MTJ) containing device is provided in which a conformal dielectric encapsulation liner is located on a sidewall of each of a MTJ pillar and an overlying top electrode, and a non-conformal dielectric encapsulation liner is located on the conformal dielectric encapsulation liner. This dual encapsulation liner structure prevents the bottom electrode of the MTJ containing device from being physically exposed thus eliminating the possibility that the bottom electrode can be a source of resputtered conductive metal particles that can deposit on a sidewall of the MTJ pillar. As such, electrical shorting is reduced in the MTJ containing device of the present application. Also, the dual encapsulation liner structure can mitigate chemical diffusion into the tunnel barrier material of the MTJ pillar.

Abstract: A bottom electrode structure for a magnetic tunnel junction (MTJ) containing device is provided. The bottom electrode structure includes a mesa portion that is laterally surrounded by a recessed region. The recessed region of the bottom electrode structure is laterally adjacent to a dielectric material, and a MTJ pillar is located on the mesa portion of the bottom electrode structure. Such a configuration shields the recessed region from impinging ions thus preventing deposition of resputtered conductive metal particles from the bottom electrode onto the MTJ pillar.

Abstract: A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains.