Patents by Inventor Bruce B. Doris

Bruce B. Doris has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Magnetic inductor with multiple magnetic layer thicknesses
    Patent number: 10593449
    Abstract: Embodiments are directed to a method of forming a laminated magnetic inductor and resulting structures having multiple magnetic layer thicknesses. A first magnetic stack having one or more magnetic layers alternating with one or more insulating layers is formed in a first inner region of the laminated magnetic inductor. A second magnetic stack is formed opposite a major surface of the first magnetic stack in an outer region of the laminated magnetic inductor. A third magnetic stack is formed opposite a major surface of the second magnetic stack in a second inner region of the laminated magnetic inductor. The magnetic layers are formed such that a thickness of a magnetic layer in each of the first and third magnetic stacks is less than a thickness of a magnetic layer in the second magnetic stack.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: March 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • CONTACT VIA STRUCTURES
    Publication number: 20200083426
    Abstract: Back end of line (BEOL) metallization structures and methods generally includes forming a landing pad on an interconnect structure. A multilayer structure including layers of metals and at least one insulating layer are provided on the structure and completely cover the landing pad. The landing pad is a metal-filled via and has a width dimension that is smaller than the multilayer structure, or the multilayer structure and the underlying metal conductor in the interconnect structure. The landing pad metal-filled via can have a width dimension that is sub-lithographic.
    Type: Application
    Filed: September 11, 2018
    Publication date: March 12, 2020
    Inventors: Chih-Chao YANG, Daniel C. EDELSTEIN, Bruce B. DORIS, Henry K. UTOMO, Theodorus E. STANDAERT, Nathan P. MARCHACK
  • DIELECTRIC ISOLATED FIN WITH IMPROVED FIN PROFILE
    Publication number: 20200083374
    Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Kangguo Cheng, Bruce B. Doris, Darsen D. Lu, Ali Khakifirooz, Kern Rim
  • STRUCTURE AND METHOD TO FABRICATE HIGHLY REACTIVE PHYSICAL VAPOR DEPOSITION TARGET
    Publication number: 20200080191
    Abstract: A physical vapor deposition (PVD) target that includes a body composed of material that is reactive with an oxygen containing atmosphere; and a non-reactive cap layer encapsulating at least a sputter surface of the body. The non-reactive cap layer is a barrier obstructing the diffusion of oxygen containing species to the body of the PVD target.
    Type: Application
    Filed: November 13, 2019
    Publication date: March 12, 2020
    Inventors: Stephen L. Brown, Bruce B. Doris, Mark C. Reuter
  • CONTACT VIA STRUCTURES
    Publication number: 20200083436
    Abstract: Back end of line (BEOL) metallization structures and methods generally includes forming a landing pad on an interconnect structure. A multilayer structure including layers of metals and at least one insulating layer are provided on the structure and completely cover the landing pad. The landing pad is a metal-filled via and has a width dimension that is smaller than the multilayer structure, or the multilayer structure and the underlying metal conductor in the interconnect structure. The landing pad metal-filled via can have a width dimension that is sub-lithographic.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 12, 2020
    Inventors: Chih-Chao YANG, Daniel C. EDELSTEIN, Bruce B. DORIS, Henry K. UTOMO, Theodorus E. STANDAERT, Nathan P. MARCHACK
  • On-chip biosensors with nanometer scale glass-like carbon electrodes and improved adhesive coupling
    Patent number: 10585060
    Abstract: Embodiments of the invention are directed to a biosensing integrated circuit (IC). A non-limiting example of the biosensing IC includes a plurality of semiconductor substrate layers. A sensor element is formed over a first one of the plurality of semiconductor substrate layers, wherein the sensor element is configured to, based at least in part on the sensor element interacting with a predetermined material, generate data representing a measureable electrical parameter. An adhesion enhancement region is configured to physically couple the sensor element to the first one of the plurality of semiconductor substrate layers. In some embodiments of the invention, the biosensing IC further includes an electrically conductive interconnect network configured to communicatively couple the data representing the measureable electrical parameter to computer elements.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hariklia Deligianni, Bruce B. Doris, Damon B. Farmer, Steven J. Holmes, Qinghuang Lin, Nathan P. Marchack, Deborah A. Neumayer, Roy R. Yu
  • ORIENTATION ENGINEERING IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR FIN FIELD EFFECT TRANSISTOR INTEGRATION FOR INCREASED MOBILITY AND SHARPER JUNCTION
    Publication number: 20200075598
    Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.
    Type: Application
    Filed: November 4, 2019
    Publication date: March 5, 2020
    Inventors: CHIA-YU CHEN, BRUCE B. DORIS, HONG HE, RAJASEKHAR VENIGALLA
  • ATOMIC LAYER DEPOSITION SEALING INTEGRATION FOR NANOSHEET COMPLEMENTARY METAL OXIDE SEMICONDUCTOR WITH REPLACEMENT SPACER
    Publication number: 20200066508
    Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Inventors: Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Structure and method to fabricate highly reactive physical vapor deposition target
    Patent number: 10570504
    Abstract: A physical vapor deposition (PVD) target that includes a body composed of material that is reactive with an oxygen containing atmosphere; and a non-reactive cap layer encapsulating at least a sputter surface of the body. The non-reactive cap layer is a barrier obstructing the diffusion of oxygen containing species to the body of the PVD target.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen L. Brown, Bruce B. Doris, Mark C. Reuter
  • Stress control in magnetic inductor stacks
    Patent number: 10573444
    Abstract: A magnetic laminating structure and process for preventing substrate bowing include multiple film stack segments that include a first magnetic layer, at least one additional magnetic layer, and a dielectric spacer disposed between the first and at least one additional magnetic layers. A dielectric isolation layer is intermediate magnetic layers and on the sidewalls thereof. The magnetic layers are characterized by defined tensile strength and the multiple segments function to relive the stress as the magnetic laminating structure is formed, wherein the cumulative thickness of the magnetic layers is greater than 1 micron. Also described are methods for forming the magnetic laminating structure.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Hariklia Deligianni, Eugene J. O'Sullivan, Naigang Wang
  • REMOVING A RESIDUAL PHOTO-MASK FENCE IN PHOTOLITHOGRAPHY
    Publication number: 20200038918
    Abstract: A first material is filled during a semiconductor fabrication process in a space bound on at least one side by a fence formation created as a result of an etching operation. A solvent-removable material is deposited such that the solvent-removable material encapsulates at least that portion of the fence formation which is protruding from the structure such that a height of the fence formation exceeds a height of the structure. The portion of the fence formation which is protruding from the structure and a first portion of the solvent-removable material are removed by planarization. A second portion of the solvent-removable material is removed by dissolving in a solvent, the second portion remaining after removal by the planarization of the first portion of the solvent-removable material.
    Type: Application
    Filed: October 7, 2019
    Publication date: February 6, 2020
    Applicant: International Business Machines Corporation
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • MAGNETIC INDUCTOR WITH SHAPE ANISOTROPHY
    Publication number: 20200035394
    Abstract: Embodiments are directed to a method of forming a laminated magnetic inductor and resulting structures having anisotropic magnetic layers. A first magnetic stack is formed having one or more magnetic layers alternating with one or more insulating layers. A trench is formed in the first magnetic stack oriented such that an axis of the trench is perpendicular to a hard axis of the magnetic inductor. The trench is filled with a dielectric material.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • MEDICAL DEVICE FOR STIMULATING AND SENSING BIOACTIVITY
    Publication number: 20200033322
    Abstract: In an approach, a biomedical device comprises at least one electrode, wherein the at least one electrode is coupled with a computer chip; at least two chemical sensors, wherein the at least two chemical sensors are coupled with the computer chip; the computer chip, wherein the computer chip comprises: a semiconductor substrate, and a processor; a microfluidic structure, wherein the microfluidic structure is an inert elastomeric polymer; a power supply device coupled to the computer chip; and an antenna configured to send data collected onto the computer chip to a remote server. In an approach, a processor stimulating a cell sample. A processor senses the presence of at least two types of biomolecules released by the cell sample. A processor records data collected by the at least two chemical sensors. A processor sends the recorded data to a remote server.
    Type: Application
    Filed: July 26, 2018
    Publication date: January 30, 2020
    Inventors: Harikilia Deligianni, Bruce B. Doris, Steven J. Holmes, Emily R. Kinser, Qinghuang Lin
  • LAMINATED MAGNETIC INDUCTOR STACK WITH HIGH FREQUENCY PEAK QUALITY FACTOR
    Publication number: 20200032383
    Abstract: Embodiments are directed to a method of forming a magnetic stack arrangement of a laminated magnetic inductor having a high frequency peak quality factor (Q). A first magnetic stack is formed having one or more magnetic layers alternating with one or more insulating layers in a first inner region of a laminated magnetic inductor. A second magnetic stack is formed opposite a surface of the first magnetic stack in an outer region of the laminated magnetic inductor. A third magnetic stack is formed opposite a surface of the second magnetic stack in a second inner region of the laminated magnetic inductor. The insulating layers are formed such that a thickness of an insulating layer in the second magnetic stack is greater than a thickness of an insulating layer in the first magnetic stack.
    Type: Application
    Filed: October 3, 2019
    Publication date: January 30, 2020
    Inventors: Hariklia Deligianni, Bruce B. Doris, Eugene J. O'Sullivan, Naigang Wang
  • Dielectric isolated fin with improved fin profile
    Patent number: 10546955
    Abstract: A method of forming a fin structure that includes forming a plurality of fin structures from a bulk semiconductor substrate and forming a dielectric spacer on a sidewall of each fin structure in the plurality of fin structure. A semiconductor spacer is formed on a sidewall of the dielectric spacer. A dielectric fill is formed in the space between the adjacent fin structures. The semiconductor spacer and a portion of the fin structures that is present below a lower surface of the dielectric spacer are oxidized. Oxidizing a base portion of the fin structures produces a first strain and oxidizing the semiconductor spacer produces a second strain that is opposite the first strain.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Darsen D. Lu, Ali Khakifirooz, Kern Rim
  • Orientation engineering in complementary metal oxide semiconductor fin field effect transistor integration for increased mobility and sharper junction
    Patent number: 10529717
    Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: January 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chia-Yu Chen, Bruce B. Doris, Hong He, Rajasekhar Venigalla
  • BIOSENSOR ELECTRODE HAVING THREE-DIMENSIONAL STRUCTURED SENSING SURFACES
    Publication number: 20200003727
    Abstract: Embodiments of the invention include a method of using a sensor. The method includes accessing a sample and exposing the sample to the sensor. The sensor includes a sensing circuit having with a field effect transistor (FET) having a gate structure. A cavity is formed in a fill material that is over the gate structure. A probe of the sensor is within a portion of the cavity. An upper region of the probe is above a top surface of the fill material, and a lower region of the probe is below the top surface of the fill material. The probe structure includes a 3D sensing surface structure, and a liner is formed on the 3D sensing surface and configured to function as a recognition element. A portion of the liner is on the lower region of the probe and positioned between sidewalls of the cavity and the 3D sensing surface.
    Type: Application
    Filed: August 13, 2019
    Publication date: January 2, 2020
    Inventors: Bruce B. Doris, Eugene J. O'Sullivan, Sufi Zafar
  • Atomic layer deposition sealing integration for nanosheet complementary metal oxide semiconductor with replacement spacer
    Patent number: 10522342
    Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: December 31, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Extra gate device for nanosheet
    Patent number: 10515859
    Abstract: A method for forming semiconductor devices includes forming a highly doped region. A stack of alternating layers is formed on the substrate. The stack is patterned to form nanosheet structures. A dummy gate structure is formed over and between the nanosheet structures. An interlevel dielectric layer is formed. The dummy gate structures are removed. SG regions are blocked, and top sheets are removed from the nanosheet structures along the dummy gate trench. A bottommost sheet is released and forms a channel for a field effect transistor device by etching away the highly doped region under the nanosheet structure and layers in contact with the bottommost sheet. A gate structure is formed in and over the dummy gate trench wherein the bottommost sheet forms a device channel for the EG device.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: December 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Terence B. Hook, Junli Wang
  • ORIENTATION ENGINEERING IN COMPLEMENTARY METAL OXIDE SEMICONDUCTOR FIN FIELD EFFECT TRANSISTOR INTEGRATION FOR INCREASED MOBILITY AND SHARPER JUNCTION
    Publication number: 20190378840
    Abstract: A semiconductor device that includes at least one germanium containing fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. The semiconductor device also includes at least one germanium free fin structure having a length along a <100> direction and a sidewall orientated along the (100) plane. A gate structure is present on a channel region of each of the germanium containing fin structure and the germanium free fin structure. N-type epitaxial semiconductor material having a square geometry present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium free fin structures. P-type epitaxial semiconductor material having a square geometry is present on the source and drain portions of the sidewalls having the (100) plane orientation of the germanium containing fin structures.
    Type: Application
    Filed: August 22, 2019
    Publication date: December 12, 2019
    Inventors: CHIA-YU CHEN, BRUCE B. DORIS, HONG HE, RAJASEKHAR VENIGALLA