Abstract: An integrated circuit includes a control circuit and a one-time programmable circuit. The control circuit determines if the one-time programmable circuit is programmed in response to an attempt to access a mode of the integrated circuit after the integrated circuit powers up. The control circuit generates a signal to indicate to a user of the integrated circuit that the mode of the integrated circuit has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the mode of the integrated circuit.

Abstract: An integrated circuit includes a control circuit and a one-time programmable circuit. The control circuit determines if the one-time programmable circuit is programmed in response to an attempt to access a mode of the integrated circuit after the integrated circuit powers up. The control circuit generates a signal to indicate to a user of the integrated circuit that the mode of the integrated circuit has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the mode of the integrated circuit.

Abstract: Logic elements (LE) that can provide a number of features. For example, the LE can provide efficient and flexible use of look up tables (LUTs) and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality to provide various modes of operation that enable the various features of the LE.

Abstract: An integrated circuit having a Physically Unclonable Function (PUF) circuit is provided. The PUF circuit may reside as part of a secure subsystem, which also includes a random number generator, a syndrome generator, non-volatile memory, and control circuitry. A predetermined syndrome of a desired PUF response is stored in the non-volatile memory. During normal operation, a current PUF response may be read out from the PUF circuit. The current PUF response may include erroneous bits that differ from the desired PUF response. The random number generator may generator a random number that masks the current PUF response, whereas the syndrome generator outputs a syndrome of the current PUF response. This information may then be passed to a separate error-correcting code (ECC) processor. The ECC processor may return information back to the secure subsystem, and the control circuitry may then obtain a corrected PUF response that matches the desired PUF response.

Abstract: An integrated circuit includes a control circuit, a one-time programmable circuit, and a security feature. The control circuit determines if the one-time programmable circuit is programmed in response to a request by a user of the integrated circuit to access the security feature. The control circuit generates a signal to indicate to the user of the integrated circuit that the security feature has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the security feature. The control circuit causes the one-time programmable circuit to be programmed in response to the request if the control circuit determines that the one-time programmable circuit has not been programmed.

Abstract: Integrated circuits may be programmed using configuration data to implement desired custom logic functions. The configuration data may be generated using a logic design system in the form of a configuration bit stream. The logic design system may generate a hash value for the stream by performing multiple hashing operations on the stream in a direction from a trailing end to a leading end of the stream in a reverse direction with respect to the order of the stream. The system may append the generated hash value to the leading end of the stream, may encrypt the hash value, and may provide the stream to an integrated circuit. The integrated circuit may decrypt or otherwise authenticate the hash value, may generate multiple test hash values for the stream and may compare the test hash values to hash values in the stream to determine whether the stream is authentic.

Abstract: An integrated circuit having a Physically Unclonable Function (PUF) circuit is provided. The PUF circuit may reside as part of a secure subsystem, which also includes a random number generator, a syndrome generator, non-volatile memory, and control circuitry. A predetermined syndrome of a desired PUF response is stored in the non-volatile memory. During normal operation, a current PUF response may be read out from the PUF circuit. The current PUF response may include erroneous bits that differ from the desired PUF response. The random number generator may generator a random number that masks the current PUF response, whereas the syndrome generator outputs a syndrome of the current PUF response. This information may then be passed to a separate error-correcting code (ECC) processor. The ECC processor may return information back to the secure subsystem, and the control circuitry may then obtain a corrected PUF response that matches the desired PUF response.

Abstract: An integrated circuit includes a control circuit, a one-time programmable circuit, and a security feature. The control circuit determines if the one-time programmable circuit is programmed in response to a request by a user of the integrated circuit to access the security feature. The control circuit generates a signal to indicate to the user of the integrated circuit that the security feature has been previously accessed if the control circuit determines that the one-time programmable circuit has been programmed to indicate a previous access to the security feature. The control circuit causes the one-time programmable circuit to be programmed in response to the request if the control circuit determines that the one-time programmable circuit has not been programmed.

Abstract: An integrated circuit having a Physically Unclonable Function (PUF) circuit is provided. The PUF circuit may be part of a secure subsystem, which also includes a random number generator, a syndrome generator, non-volatile memory, and control circuitry. A predetermined syndrome of a desired PUF response is stored in the non-volatile memory. During normal operation, a current PUF response may be read out from the PUF circuit. The current PUF response may differ from the desired PUF response. The random number generator may generate a random number that masks the current PUF response, whereas the syndrome generator outputs a syndrome of the current PUF response. This information may then be passed to an error-correcting code (ECC) processor. The ECC processor may return information to the secure subsystem. The control circuitry may then obtain a corrected PUF response that matches the desired PUF response.

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Abstract: A method for managing records in an object-oriented database is disclosed. Modified representations of data in fields of records is generated in response to patterns in the data. The modified representations of the data is compressed utilizing similarities in the modified representations of the data.

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.

Abstract: A method for managing records in an object-oriented database is disclosed. Modified representations of data in fields of records is generated in response to patterns in the data. The modified representations of the data is compressed utilizing similarities in the modified representations of the data.

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.

Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

Abstract: A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.

Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.

Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.