Patents by Inventor Bruce Pedersen
Bruce Pedersen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20070222477Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexes with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.Type: ApplicationFiled: May 24, 2007Publication date: September 27, 2007Inventors: David Lewis, Bruce Pedersen, Sinan Kaptanoglu, Andy Lee
-
Patent number: 7262635Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.Type: GrantFiled: September 1, 2006Date of Patent: August 28, 2007Assignee: Altera CorporationInventors: James Schleicher, Jim Park, Sergey Shumarayev, Bruce Pedersen, Tony Ngai, Wei-Jen Huang, Victor Maruri, Rakesh Patel
-
Patent number: 7253660Abstract: A multiplexing device is described. In one embodiment, the multiplexing device includes: a hardwired multiplexer including a plurality of input terminals; a plurality of select terminals; and at least one output terminal, where the plurality of input terminals are coupled to a plurality of block input lines or a plurality of functional element input terminals. In one embodiment, the plurality of input terminals are hardwired to the plurality of block input lines or the plurality of functional element input terminals. In one embodiment, the plurality of select terminals are coupled to a second plurality of functional element input terminals or a plurality of functional element output terminals. In one embodiment, the plurality of block input lines include a plurality of logic array block (LAB) lines, the plurality of functional element input terminals include a plurality of logic element (LE) input terminals, and the plurality of functional element output terminals include LE output terminals.Type: GrantFiled: November 27, 2002Date of Patent: August 7, 2007Assignee: Altera CorporationInventors: Paul Leventis, Bruce Pedersen, Chris Lane, Srinivas Reddy, David Lewis
-
Patent number: 7249339Abstract: A method for improving a design on a field programmable gate array (FPGA) includes modifying the design in response to a unate characteristic of an input to a node on the FPGA, and rising and falling delays of a node feeding the input.Type: GrantFiled: August 16, 2004Date of Patent: July 24, 2007Assignee: Altera CorporationInventor: Bruce Pedersen
-
Patent number: 7218133Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.Type: GrantFiled: February 2, 2005Date of Patent: May 15, 2007Assignee: Altera CorporationInventors: David M. Lewis, Paul Leventis, Andy L. Lee, Henry Kim, Bruce Pedersen, Chris Wysocki, Christopher F. Lane, Alexander Marquardt, Vikram Santurkar, Vaughn Timothy Betz
-
Publication number: 20070080710Abstract: A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.Type: ApplicationFiled: September 1, 2006Publication date: April 12, 2007Inventors: James Schleicher, Jim Park, Sergey Shumarayev, Bruce Pedersen, Tony Ngai, Wei-Jen Huang, Victor Maruri, Rakesh Patel
-
Publication number: 20070069764Abstract: A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.Type: ApplicationFiled: September 26, 2006Publication date: March 29, 2007Inventors: David Lewis, Vaughn Betz, Irfan Rahim, Peter McElheny, Yow-Juang Liu, Bruce Pedersen
-
Publication number: 20070063732Abstract: A fracturable logic element includes a first, second, third, and fourth two-input lookup tables (2-LUTs). Each 2-LUT includes four memory elements. Each memory element is configured to hold one data bit. The fracturable logic element also includes a set of six inputs and a control circuit configured to operate in a first mode and a second mode. When the control circuit operates in the first mode, a first combinatorial output is generated using four of the set of six inputs and the first, second, third, and fourth 2-LUTs. When the control circuit operates in the second mode, a second combinatorial output is generated using a first subset of three of the set of six inputs and the first and second 2-LUTS. Additionally, when the control circuit operates in the second mode, a third combinatorial output is generated using a second subset of three of the set of six inputs and the third and fourth 2-LUTs, the first and second subsets being non-intersecting subsets of the set of six inputs.Type: ApplicationFiled: September 22, 2005Publication date: March 22, 2007Applicant: Altera CorporationInventors: Sinan Kaptanoglu, Bruce Pedersen, James Schleicher, Jinyong Yuan, Michael Hutton, David Lewis
-
Patent number: 7185035Abstract: According to some embodiments, arithmetic structures in logic elements result from combining inverters and pass gates (or other multiplexing hardware) with LUT hardware. According to other embodiments, arithmetic structures in logic elements result from combining dedicated adder hardware (e.g., including XOR units) and fracturable LUT hardware. According to other embodiments, arithmetic structures in logic elements result from providing complementary input connections between multiplexers and LUT hardware. In this way, the present invention enables the incorporation of arithmetic structures with LUT structures in a number of ways.Type: GrantFiled: October 23, 2003Date of Patent: February 27, 2007Assignee: Altera CorporationInventors: David Lewis, Bruce Pedersen, Sinan Kaptanoglu
-
Patent number: 7176718Abstract: A programmable logic element grouping for use in multiple instances on a programmable logic device includes more than the traditional number of logic elements sharing secondary signal (e.g., clock, clock enable, clear, etc.) selection circuitry. The logic elements in such a grouping are divided into at least two subgroups. Programmable interconnection circuitry is provided for selectively applying signals from outside the grouping and signals fed back from the logic elements in the grouping to primary inputs of the logic elements in the grouping. The programmable interconnection circuitry limits possible application of at least some of these signals to one or the other of the subgroups, and/or provides for possible application of at least some of these signals to a greater percentage of the primary inputs to one of the subgroups than to the other.Type: GrantFiled: January 21, 2005Date of Patent: February 13, 2007Assignee: Altera CorporationInventors: Michael D Hutton, Bruce Pedersen, Sinan Kaptanoglu, David Lewis, Tim Vanderhoek
-
Publication number: 20070030029Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.Type: ApplicationFiled: November 7, 2005Publication date: February 8, 2007Inventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Victor Maruri, Rakesh Patel
-
Patent number: 7167022Abstract: Disclosed is an LE that can provide a number of advantageous feature. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.Type: GrantFiled: March 25, 2004Date of Patent: January 23, 2007Assignee: Altera CorporationInventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy Lee, Rahul Saini, Henry Kim
-
Publication number: 20060294293Abstract: Circuits and methods for providing versatile RAM for a programmable logic device are provided. These circuits and methods preferably allow signal lines that may be used to provide inputs for logic elements to be used instead for addressing memory blocks that form the versatile RAM.Type: ApplicationFiled: August 28, 2006Publication date: December 28, 2006Inventor: Bruce Pedersen
-
Patent number: 7129745Abstract: A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.Type: GrantFiled: June 10, 2004Date of Patent: October 31, 2006Assignee: Altera CorporationInventors: David Lewis, Vaughn Betz, Irfan Rahim, Peter McElheny, Yow-Juang W. Liu, Bruce Pedersen
-
Patent number: 7119575Abstract: Logic circuits that provide improved efficiency are described. In one general embodiment, this is accomplished by feeding outputs of LEs in the logic circuit to multiplexers that receive their select signals from input terminals of the LEs in the logic circuit. In one embodiment, each of the LEs provides one output signal. The first LE in the logic circuit provides an output signal to one multiplexer, while each of the remaining LEs in the logic circuit provides an output signal to two multiplexers. In another embodiment, each of the LEs provides two output signals. The first LE in the logic circuit provides two output signals to one multiplexer, while each of the remaining LEs in the logic circuit provides two output signals to four multiplexers.Type: GrantFiled: January 12, 2004Date of Patent: October 10, 2006Assignee: Altera CorporationInventors: James Schleicher, Bruce Pedersen, Sinan Kaptanoglu
-
Patent number: 7100141Abstract: A technique of minimizes circuit area on programmable logic with fracturable logic elements by using “balancing” in the technology mapping stage of the programmable logic computer-aided-design flow. A fracturable LE can be used for logic implementation in many ways, such as being used as one maximum-sized look-up table (LUT) or multiple smaller LUTs. One of more inputs of the multiple smaller LUTs may be shared. By balancing, this means mean that the technology mapping algorithm is tuned to use more small LUTs and fewer maximum-sized LUTs to implement the circuit. Although this is counterintuitive since the larger LUTs are more effective at absorbing gates, the technique achieves a smaller final circuit area by packing small LUTs into fracturable LEs.Type: GrantFiled: December 23, 2003Date of Patent: August 29, 2006Assignee: Altera CorporationInventors: Boris Ratchev, Yean-Yow Hwang, Bruce Pedersen
-
Patent number: 7061268Abstract: A logic circuit includes a first series of logic elements. Each logic element has a look-up table (LUT) and a dedicated adder to implement an arithmetic mode in the logic element. The logic circuit also includes a carry chain connecting the first series of logic element, and an initialization circuit connected to the carry chain to initialize the carry chain.Type: GrantFiled: March 15, 2004Date of Patent: June 13, 2006Assignee: Altera CorporationInventors: Andy L. Lee, Ninh Ngo, Vaughn Betz, David Lewis, Bruce Pedersen, James Schleicher
-
Patent number: 7042247Abstract: The number of off and possibly leaking transistors in circuitry such as look-up table (LUT) circuitry is reduced by dividing the LUT or LUT-type circuitry into two separate or at least partly separate circuits. One of these circuits operates on first manifestations of the signals selectable by the circuitry. The other circuit operates on electrically different second manifestations of the selectable signals. Selections made by the two circuits are combined to produce an output of the circuitry.Type: GrantFiled: August 12, 2004Date of Patent: May 9, 2006Assignee: Altera CorporationInventor: Bruce Pedersen
-
Patent number: 7030650Abstract: Disclosed is a configurable logic circuit that includes at least 6 inputs and at least two outputs. The configurable logic element can carry out only a subset of all 6-input logic functions and, thus, requires a substantially smaller silicon area than a 6-LUT that can perform all 6-input logic functions. Also, the configurable logic circuit can be configured such that a first subset of the inputs drive one of the outputs and a second subset of the inputs drive another output.Type: GrantFiled: November 10, 2004Date of Patent: April 18, 2006Assignee: Altera CorporationInventors: Sinan Kaptanoglu, David Lewis, Bruce Pedersen
-
Patent number: 6995590Abstract: A circuit is provided that aligns the phase of a delay signal with an input clock signal. The circuit functions as a phase locked loop (PLL) in a first state of operation and as a delay locked loop (DLL) in a second state of operation. An adjustable delay circuit generates the delay signal. A phase detector compares the input clock signal to the delay signal to generate a phase detection signal. The adjustable delay circuit adjusts the phase of the delay signal in response to the phase detection signal. A multiplexer couples the delay signal back to the input of the adjustable delay circuit using a feedback loop in the first state of operation. The multiplexer couples the input clock signal to the input of the adjustable delay circuit in the second state of operation.Type: GrantFiled: September 22, 2003Date of Patent: February 7, 2006Assignee: Altera CorporationInventor: Bruce Pedersen