Patents by Inventor Bruce Pedersen

Bruce Pedersen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7757189
    Abstract: Redundant elements of digital designs, including digital designs with registered feedback, are identified and removed. The nodes of a design are assigned initial labels. The design is analyzed by selecting nodes associated with each label and identifying any equivalent nodes or complementary nodes to the selected node. Nodes are equivalent if they perform the same or complementary functions on input nodes assigned to the same labels. The selected node and its equivalent node, if any, are reassigned to the same label. Two or more complementary nodes are modified so that they have the same output. This analysis is repeated until all of the labels and associated nodes have been analyzed and there are no labels and associated nodes in need of further analysis. Following this analysis, equivalent nodes in the digital design will share the same label and all but one node with each label can be removed.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: July 13, 2010
    Assignee: Altera Corporation
    Inventors: Bruce Pedersen, Greg William Baeckler
  • Patent number: 7671625
    Abstract: Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: March 2, 2010
    Assignee: Altera Corporation
    Inventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Michael Hutton, Andy Lee, Rahul Saini, Henry Kim
  • Patent number: 7671626
    Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: March 2, 2010
    Assignee: Altera Corporation
    Inventors: David M. Lewis, Paul Leventis, Andy L. Lee, Henry Kim, Bruce Pedersen, Chris Wysocki, Christopher F. Lane, Alexander Marquardt, Vikram Santurkar, Vaughn Betz
  • Publication number: 20090289660
    Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.
    Type: Application
    Filed: January 20, 2009
    Publication date: November 26, 2009
    Inventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
  • Publication number: 20090289696
    Abstract: A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
    Type: Application
    Filed: July 31, 2009
    Publication date: November 26, 2009
    Inventors: David Lewis, Vaughn Betz, Irfan Rahim, Peter McElheny, Yow-Juang W. Liu, Bruce Pedersen
  • Patent number: 7573317
    Abstract: A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.
    Type: Grant
    Filed: September 26, 2006
    Date of Patent: August 11, 2009
    Assignee: Altera Corporation
    Inventors: David Lewis, Vaughn Betz, Irfan Rahim, Peter McElheny, Yow-Juang W. Liu, Bruce Pedersen
  • Patent number: 7538579
    Abstract: Disclosed is an LE that can provide a number of advantageous features. For example, the LE can provide efficient and flexible use of LUTs and input sharing. The LE may also provide for flexible use of one or more dedicated adders and include register functionality.
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: May 26, 2009
    Assignee: Altera Corporation
    Inventors: James Schleicher, Richard Yuan, Bruce Pedersen, Sinan Kaptanoglu, Gregg Baeckler, David Lewis, Mike Hutton, Andy Lee, Rahul Saini, Henry Kim
  • Patent number: 7492188
    Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: February 17, 2009
    Assignee: Altera Corporation
    Inventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter J. Kazarian, Andrew Leaver, David W. Mendel, Jim Park
  • Patent number: 7441223
    Abstract: A method for designing a system on a programmable logic device (PLD) includes implementing a first network of logic elements (LEs) and a second network of LEs with a combined network of LEs that performs a same functionality but utilizes a fewer number of LEs.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: October 21, 2008
    Assignee: Altera Corporation
    Inventor: Bruce Pedersen
  • Patent number: 7432734
    Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: October 7, 2008
    Assignee: Altera Corporation
    Inventors: David M. Lewis, Paul Leventis, Andy L. Lee, Henry Kim, Bruce Pedersen, Chris Wysocki, Christopher F. Lane, Alexander Marquardt, Vikram Santurkar, Vaughn Betz
  • Patent number: 7406668
    Abstract: Implementation of a logic design in either an FPGA or a structured ASIC is facilitated by designing either type of implementation so that it takes into account the possible need to migrate the design to the other type of implementation. Portions of the design that are being considered for one type of implementation (e.g., FPGA implementation) are assessed for suitability and/or desirability based not only on their suitability/desirability in that one type of implementation, but also based on their suitability/desirability in the other type of implementation (e.g., structured ASIC implementation).
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: July 29, 2008
    Assignee: Altera Corporation
    Inventors: Bruce Pedersen, Jinyong Yuan
  • Publication number: 20080164936
    Abstract: A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).
    Type: Application
    Filed: March 24, 2008
    Publication date: July 10, 2008
    Inventors: Irfan Rahim, Peter McElheny, Yow-Juang W. Liu, Bruce Pedersen
  • Patent number: 7368944
    Abstract: A programmable logic element grouping for use in multiple instances on a programmable logic device includes more than the traditional number of logic elements sharing secondary signal (e.g., clock, clock enable, clear, etc.) selection circuitry. The logic elements in such a grouping are divided into at least two subgroups. Programmable interconnection circuitry is provided for selectively applying signals from outside the grouping and signals fed back from the logic elements in the grouping to primary inputs of the logic elements in the grouping. The programmable interconnection circuitry limits possible application of at least some of these signals to one or the other of the subgroups, and/or provides for possible application of at least some of these signals to a greater percentage of the primary inputs to one of the subgroups than to the other.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: May 6, 2008
    Assignee: Altera Corporation
    Inventors: Michael D. Hutton, Bruce Pedersen, Sinan Kaptanoglu, David Lewis, Tim Vanderhoek
  • Publication number: 20080074143
    Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.
    Type: Application
    Filed: July 30, 2007
    Publication date: March 27, 2008
    Inventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Michael Hutton, Victor Maruri, Rakesh Patel, Peter Kazarian, Andrew Leaver, David Mendel, Jim Park
  • Patent number: 7348827
    Abstract: A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator sets the body bias of the transistor(s) so as to trade off performance and power consumption of the transistor(s).
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: March 25, 2008
    Assignee: Altera Corporation
    Inventors: Irfan Rahim, Peter McElheny, Yow-Juang W. Liu, Bruce Pedersen
  • Patent number: 7323902
    Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: January 29, 2008
    Assignee: Altera Corporation
    Inventors: David Lewis, Bruce Pedersen, Sinan Kaptanoglu, Andy L. Lee
  • Patent number: 7317330
    Abstract: A particular embodiment of the present invention provides a shared-LUT logic circuit that provides the functionality of two (n+1)LUT logic circuits without requiring approximately twice the resources of two nLUT circuits. In some embodiments, a shared-LUT logic circuit is provided that can be configured to operate in multiple modes including, for example, an nLUT mode, an (n+1)LUT mode, and other modes.
    Type: Grant
    Filed: July 14, 2004
    Date of Patent: January 8, 2008
    Assignee: Altera Corporation
    Inventor: Bruce Pedersen
  • Patent number: 7317332
    Abstract: A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: January 8, 2008
    Assignee: Altera Corporation
    Inventors: Tony Ngai, Bruce Pedersen, Sergey Shumarayev, James Schleicher, Wei-Jen Huang, Victor Maruri, Rakesh Patel
  • Patent number: 7312632
    Abstract: A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: December 25, 2007
    Assignee: Altera Corporation
    Inventors: David Lewis, Bruce Pedersen, Sinan Kaptanoglu, Andy Lee
  • Publication number: 20070252617
    Abstract: An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB.
    Type: Application
    Filed: May 2, 2007
    Publication date: November 1, 2007
    Inventors: David Lewis, Paul Leventis, Andy Lee, Henry Kim, Bruce Pedersen, Chris Wysocki, Christopher Lane, ALexander Marquardt, Vikram Santurkar, Vaughn Betz