Abstract: One embodiment provides a graphics processor including a processing resource including a register file, memory, a cache memory, and load/store/cache circuitry to process load, store, and prefetch messages from the processing resource. The circuitry includes support for an immediate address offset that will be used to adjust the address supplied for a memory access to be requested by the circuitry. Including support for the immediate address offset removes the need to execute additional instructions to adjust the address to be accessed prior to execution of the memory access instruction.

Abstract: An apparatus and method to execute ray tracing instructions. For example, one embodiment of an apparatus comprises execution circuitry to execute a dequantize instruction to convert a plurality of quantized data values to a plurality of dequantized data values, the dequantize instruction including a first source operand to identify a plurality of packed quantized data values in a source register and a destination operand to identify a destination register in which to store a plurality of packed dequantized data values, wherein the execution circuitry is to convert each packed quantized data value in the source register to a floating point value, to multiply the floating point value by a first value to generate a first product and to add the first product to a second value to generate a dequantized data value, and to store the dequantized data value in a packed data element location in the destination register.

Abstract: Apparatus and method for denoising of images generated by a rendering engine such as a ray tracing engine. For example, one embodiment of a system or apparatus comprises: A system comprising: a plurality of nodes to perform ray tracing operations; a dispatcher node to dispatch graphics work to the plurality of nodes, each node to perform ray tracing to render a region of an image frame; at least a first node of the plurality comprising: a ray-tracing renderer to perform ray tracing to render a first region of the image frame; and a denoiser to perform denoising of the first region using a combination of data associated with the first region and data associated with a region outside of the first region, at least some of the data associated with the region outside of the first region to be retrieved from at least one other node.

Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.

Abstract: An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.

Abstract: Apparatus and method for compressing an acceleration data structure such as a bounding volume hierarchy (BVH). For example, one embodiment of a graphics processing apparatus comprises: one or more cores to execute graphics instructions including instructions to perform ray tracing operations; and compression circuitry to compress lowest level nodes of a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes, each of the lowest level nodes comprising pointers to leaf data; the compression circuitry to quantize the lowest level nodes to generate quantized lowest level nodes and to store each quantized lowest level node and associated leaf data without the pointers to the leaf data.

Abstract: Apparatus and method for acceleration data structure refit. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a hierarchical acceleration data structure generator to construct an acceleration data structure comprising a plurality of hierarchically arranged nodes including inner nodes and leaf nodes stored in a memory in a depth-first search (DFS) order; traversal hardware logic to traverse one or more of the rays through the acceleration data structure; intersection hardware logic to determine intersections between the one or more rays and one or more primitives within the hierarchical acceleration data structure; a node refit unit comprising circuitry and/or logic to read consecutively through at least the inner nodes in the memory in reverse DFS order to perform a bottom-up refit operation on the hierarchical acceleration data structure.

Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.

Abstract: Apparatus and method for a hierarchical beam tracer.

Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.

Abstract: An apparatus and method for compressing ray tracing data prior to transmission between nodes. For example, one embodiment of an apparatus comprises: a first node comprising a first ray tracing engine, the first node communicatively coupled to a second node comprising a second ray tracing engine; first compression circuitry coupled to the first ray tracing engine, the first compression circuitry to perform compression on ray tracing data of the first ray tracing engine to produce a first compressed stream of ray tracing data; and interface circuitry to transmit the first compressed stream of ray tracing data from the first node to the second node.

Abstract: Cluster of acceleration engines to accelerate intersections.

Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.

Abstract: An apparatus and method are described for using tessellation hardware to generate bounding volume hierarchies (BVHs) and perform other ray tracing operations. For example, one embodiment of an apparatus comprises: a shader to output a plurality of tessellation factors and one or more input surfaces; and a tessellation circuit comprising first circuitry and/or logic to tesselate each input surface to generate a new set of primitives and second circuitry and/or logic to concurrently generate a bounding volume hierarchy (BVH) 1521 based on the new set of primitives.

Abstract: An apparatus and method for performing BVH compression and decompression concurrently with stores and loads, respectively.

Abstract: Systems, apparatuses and methods may provide for technology that assigns a first shading rate to a first region of a frame. The technology further assigns a second shading rate to a second region of the frame. The first shading rate indicates that the first region will be rendered at a first resolution, and the second shading rate indicates that the second region will be rendered at a second resolution less than the first resolution. The first and second shading rates are associated with a selection based on a motion vector that corresponds to motion of an object. The object is rendered as part of a scene that includes the first region rendered at the first resolution and the second region rendered at the second resolution.

Abstract: An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.

Abstract: An apparatus and method for efficiently reconstructing a BVH. For example, one embodiment of a method comprises: constructing an object bounding volume hierarchy (BVH) for each object in a scene, each object BVH including a root node and one or more child nodes based on primitives included in each object; constructing a top-level BVH using the root nodes of the individual object BVHs; performing an analysis of the top-level BVH to determine whether the top-level BVH comprises a sufficiently efficient arrangement of nodes within its hierarchy; and reconstructing at least a portion of the top-level BVH if a more efficient arrangement of nodes exists, wherein reconstructing comprises rebuilding the portion of the top-level BVH until one or more stopping criteria have been met, the stopping criteria defined to prevent an entire rebuilding of the top-level BVH.

Abstract: Apparatus and method for preventing re-traversal of a prior path on a restart. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; circuitry to traverse one or more of the rays through the BVH to form a current traversal path and intersect the one or more rays with primitives contained within the nodes, wherein the circuitry is to process entries from the top of a first data structure comprising entries each associated with a child node at the current BVH level, the entries being ordered from top to bottom based on a sorted distance of each respective child node.

Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.