Patents by Inventor Carsten Benthin

Carsten Benthin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11315304
    Abstract: Apparatus and method for a hierarchical beam tracer.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: April 26, 2022
    Assignee: INTEL CORPORATION
    Inventors: Scott Janus, Prasoonkumar Surti, Karthik Vaidyanathan, Alexey Supikov, Gabor Liktor, Carsten Benthin, Philip Laws, Michael Doyle
  • Patent number: 11295409
    Abstract: Apparatus and method for compressing an acceleration data structure such as a bounding volume hierarchy (BVH). For example, one embodiment of a graphics processing apparatus comprises: one or more cores to execute graphics instructions including instructions to perform ray tracing operations; and compression circuitry to compress lowest level nodes of a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes, each of the lowest level nodes comprising pointers to leaf data; the compression circuitry to quantize the lowest level nodes to generate quantized lowest level nodes and to store each quantized lowest level node and associated leaf data without the pointers to the leaf data.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: April 5, 2022
    Assignee: INTEL CORPORATION
    Inventors: Carsten Benthin, Sven Woop, Ingo Wald
  • Publication number: 20220068009
    Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 3, 2022
    Inventors: Ingo Wald, Carsten Benthin, Sven Woop
  • Patent number: 11263799
    Abstract: Cluster of acceleration engines to accelerate intersections.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: March 1, 2022
    Assignee: INTEL CORPORATION
    Inventors: Prasoonkumar Surti, Carsten Benthin, Karthik Vaidyanathan, Philip Laws, Scott Janus, Sven Woop
  • Publication number: 20220051476
    Abstract: Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.
    Type: Application
    Filed: December 23, 2020
    Publication date: February 17, 2022
    Inventors: Sven Woop, Michael J. Doyle, Sreenivas Kothandaraman, Karthik Vaidyanathan, Abhishek R. Appu, Carsten Benthin, Prasoonkumar Surti, Holger GRUEN, Stephen Junkins, Adam Lake, Bret G. Alfieri, Gabor Liktor, Joshua Barczak, Won-Jong Lee
  • Publication number: 20220051467
    Abstract: Apparatus and method for efficient graphics processing including ray tracing. For example, one embodiment of a graphics processor comprises: execution hardware logic to execute graphics commands and render images; an interface to couple functional units of the execution hardware logic to a tiled resource; and a tiled resource manager to manage access by the functional units to the tiled resource, a functional unit of the execution hardware logic to generate a request with a hash identifier (ID) to request access to a portion of the tiled resource, wherein the tiled resource manager is to determine whether a portion of the tiled resource identified by the hash ID exists, and if not, to allocate a new portion of the tiled resource and associate the new portion with the hash ID.
    Type: Application
    Filed: December 23, 2020
    Publication date: February 17, 2022
    Inventors: Sven Woop, Michael J. Doyle, Sreenivas Kothandaraman, Karthik Vaidyanathan, Abhishek R. Appu, Carsten Benthin, Prasoonkumar Surti, Holger GRUEN, Stephen Junkins, Adam Lake, Bret G. Alfieri, Gabor Liktor, Joshua Barczak, Won-Jong Lee
  • Publication number: 20220044467
    Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.
    Type: Application
    Filed: July 13, 2021
    Publication date: February 10, 2022
    Inventors: Sven WOOP, Attila AFRA, Carsten BENTHIN, Ingo WALD, Johannes GUENTHER
  • Publication number: 20220005259
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: September 22, 2021
    Publication date: January 6, 2022
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer KP, Jonathan Kennedy, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Tomer Bar-On, Carsten Benthin, Adam T. Lake, Vasanth Ranganathan, Abhishek R. Appu
  • Publication number: 20210407177
    Abstract: Apparatus and method for ray tracing acceleration using a grid primitive.
    Type: Application
    Filed: July 6, 2021
    Publication date: December 30, 2021
    Applicant: Intel Corporation
    Inventors: Scott JANUS, Prasoonkumar SURTI, Karthik VAIDYANATHAN, Carsten BENTHIN, Philip LAWS
  • Patent number: 11210841
    Abstract: An apparatus and method are described for using tessellation hardware to generate bounding volume hierarchies (BVHs) and perform other ray tracing operations. For example, one embodiment of an apparatus comprises: a shader to output a plurality of tessellation factors and one or more input surfaces; and a tessellation circuit comprising first circuitry and/or logic to tesselate each input surface to generate a new set of primitives and second circuitry and/or logic to concurrently generate a bounding volume hierarchy (BVH) 1521 based on the new set of primitives.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: December 28, 2021
    Assignee: Intel Corporation
    Inventors: Carsten Benthin, Gabor Liktor
  • Patent number: 11189074
    Abstract: An apparatus and method for efficiently reconstructing a BVH. For example, one embodiment of a method comprises: constructing an object bounding volume hierarchy (BVH) for each object in a scene, each object BVH including a root node and one or more child nodes based on primitives included in each object; constructing a top-level BVH using the root nodes of the individual object BVHs; performing an analysis of the top-level BVH to determine whether the top-level BVH comprises a sufficiently efficient arrangement of nodes within its hierarchy; and reconstructing at least a portion of the top-level BVH if a more efficient arrangement of nodes exists, wherein reconstructing comprises rebuilding the portion of the top-level BVH until one or more stopping criteria have been met, the stopping criteria defined to prevent an entire rebuilding of the top-level BVH.
    Type: Grant
    Filed: June 2, 2020
    Date of Patent: November 30, 2021
    Assignee: INTEL CORPORATION
    Inventors: Carsten Benthin, Sven Woop
  • Patent number: 11189076
    Abstract: Apparatus and method for preventing re-traversal of a prior path on a restart. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; circuitry to traverse one or more of the rays through the BVH to form a current traversal path and intersect the one or more rays with primitives contained within the nodes, wherein the circuitry is to process entries from the top of a first data structure comprising entries each associated with a child node at the current BVH level, the entries being ordered from top to bottom based on a sorted distance of each respective child node.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: November 30, 2021
    Assignee: INTEL CORPORATION
    Inventors: Karthik Vaidyanathan, Sven Woop, Carsten Benthin
  • Publication number: 20210350609
    Abstract: An apparatus and method for compressing ray tracing data prior to transmission between nodes. For example, one embodiment of an apparatus comprises: a first node comprising a first ray tracing engine, the first node communicatively coupled to a second node comprising a second ray tracing engine; first compression circuitry coupled to the first ray tracing engine, the first compression circuitry to perform compression on ray tracing data of the first ray tracing engine to produce a first compressed stream of ray tracing data; and interface circuitry to transmit the first compressed stream of ray tracing data from the first node to the second node.
    Type: Application
    Filed: April 6, 2021
    Publication date: November 11, 2021
    Inventors: Ingo WALD, Gabor LIKTOR, Carsten BENTHIN, Carson BROWNLEE, Johannes GUENTHER, Jefferson D. AMSTUTZ
  • Publication number: 20210342968
    Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.
    Type: Application
    Filed: May 17, 2021
    Publication date: November 4, 2021
    Applicant: Intel IP Corporation
    Inventors: Carsten Benthin, Sven Woop, Ingo Wald
  • Publication number: 20210287431
    Abstract: Apparatus and method for lossy displaced mesh compression. For example, one embodiment of an apparatus comprises: displacement mapping circuitry/logic to generate an original displacement-mapped mesh by performing a displacement mapping of a plurality of vertices of a base subdivision mesh; and mesh compression circuitry/logic to compress the original displacement-mapped mesh, the mesh compression circuitry/logic comprising a quantizer to quantize the displacement mapping of the plurality of vertices in view of a base mesh to generate a displacement array.
    Type: Application
    Filed: March 15, 2020
    Publication date: September 16, 2021
    Inventors: Sven WOOP, Karthik VAIDYANATHAN, Carsten BENTHIN
  • Publication number: 20210287429
    Abstract: Apparatus and method for box-box testing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged BVH nodes; traversal circuitry to traverse query boxes through the BVH, the traversal circuitry to read a BVH node from a top of a BVH node stack and to read a query box from a local storage or memory, the traversal circuitry further comprising: box-box testing circuitry and/or logic to compare maximum and minimum X, Y, and Z coordinates of the BVH node and the query box and to generate an overlap indication if overlap is detected for each of the X, Y, and Z dimensions; distance determination circuitry and/or logic to generate a distance value representing an extent of overlap between the BVH node and the query box; and sorting circuitry and/or logic to sort the BVH node within a set of one or more additional BVH nodes based on the distance value.
    Type: Application
    Filed: March 15, 2020
    Publication date: September 16, 2021
    Inventors: Karthik VAIDYANATHAN, Carsten BENTHIN, Sven WOOP
  • Publication number: 20210287428
    Abstract: Apparatus and method for processing motion blur operations. For example, one embodiment of a graphics processing apparatus comprises: a bounding volume hierarchy (BVH) generator to build a BVH comprising hierarchically-arranged BVH nodes based on input primitives, at least one BVH node comprising one or more child nodes; and motion blur processing hardware logic to determine motion values for a quantization grid based on motion values of the one or more child nodes of the at least one BVH node and to map linear bounds of each of the child nodes to the quantization grid.
    Type: Application
    Filed: March 15, 2020
    Publication date: September 16, 2021
    Inventors: Sven WOOP, Carsten BENTHIN, Karthik VAIDYANATHAN
  • Patent number: 11120608
    Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: September 14, 2021
    Assignee: INTEL CORPORATION
    Inventors: Ingo Wald, Carsten Benthin, Sven Woop
  • Publication number: 20210241431
    Abstract: Apparatus and method for denoising of images generated by a rendering engine such as a ray tracing engine. For example, one embodiment of a system or apparatus comprises: A system comprising: a plurality of nodes to perform ray tracing operations; a dispatcher node to dispatch graphics work to the plurality of nodes, each node to perform ray tracing to render a region of an image frame; at least a first node of the plurality comprising: a ray-tracing renderer to perform ray tracing to render a first region of the image frame; and a denoiser to perform denoising of the first region using a combination of data associated with the first region and data associated with a region outside of the first region, at least some of the data associated with the region outside of the first region to be retrieved from at least one other node.
    Type: Application
    Filed: February 9, 2021
    Publication date: August 5, 2021
    Inventors: Carson BROWNLEE, Ingo WALD, Attila AFRA, Johannes GUENTHER, Jefferson AMSTUTZ, Carsten BENTHIN
  • Patent number: 11069118
    Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: July 20, 2021
    Assignee: INTEL CORPORATION
    Inventors: Sven Woop, Attila Afra, Carsten Benthin, Ingo Wald, Johannes Guenther