Patents by Inventor Carsten Benthin

Carsten Benthin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200211151
    Abstract: Apparatus and method for a compressed stack representation for a BVH.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: KARTHIK VAIDYANATHAN, SVEN WOOP, CARSTEN BENTHIN
  • Publication number: 20200211231
    Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: CARSON BROWNLEE, CARSTEN BENTHIN, JOSHUA BARCZAK, KAI XIAO, MICHAEL APODACA, PRASOONKUMAR SURTI, THOMAS RAOUX
  • Patent number: 10699465
    Abstract: Cluster of acceleration engines to accelerate intersections.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Carsten Benthin, Karthik Vaidyanathan, Philip Laws, Scott Janus, Sven Woop
  • Patent number: 10699370
    Abstract: Apparatus and method for a compressed stack representation for a BVH.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Karthik Vaidyanathan, Sven Woop, Carsten Benthin
  • Publication number: 20200202493
    Abstract: Apparatus and method for denoising of images generated by a rendering engine such as a ray tracing engine. For example, one embodiment of a system or apparatus comprises: A system comprising: a plurality of nodes to perform ray tracing operations; a dispatcher node to dispatch graphics work to the plurality of nodes, each node to perform ray tracing to render a region of an image frame; at least a first node of the plurality comprising: a ray-tracing renderer to perform ray tracing to render a first region of the image frame; and a denoiser to perform denoising of the first region using a combination of data associated with the first region and data associated with a region outside of the first region, at least some of the data associated with the region outside of the first region to be retrieved from at least one other node.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Inventors: CARSON BROWNLEE, INGO WALD, ATTILA AFRA, JOHANNES GUENTHER, JEFFERSON AMSTUTZ, CARSTEN BENTHIN
  • Patent number: 10679403
    Abstract: An apparatus and method for efficiently reconstructing a BVH. For example, one embodiment of a method comprises: constructing an object bounding volume hierarchy (BVH) for each object in a scene, each object BVH including a root node and one or more child nodes based on primitives included in each object; constructing a top-level BVH using the root nodes of the individual object BVHs; performing an analysis of the top-level BVH to determine whether the top-level BVH comprises a sufficiently efficient arrangement of nodes within its hierarchy; and reconstructing at least a portion of the top-level BVH if a more efficient arrangement of nodes exists, wherein reconstructing comprises rebuilding the portion of the top-level BVH until one or more stopping criteria have been met, the stopping criteria defined to prevent an entire rebuilding of the top-level BVH.
    Type: Grant
    Filed: April 14, 2017
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: Carsten Benthin, Sven Woop
  • Publication number: 20200160583
    Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.
    Type: Application
    Filed: January 22, 2020
    Publication date: May 21, 2020
    Inventors: Sven WOOP, Attila AFRA, Carsten BENTHIN, Ingo WALD, Johannes GUENTHER
  • Publication number: 20200134776
    Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.
    Type: Application
    Filed: January 23, 2019
    Publication date: April 30, 2020
    Applicant: Intel IP Corporation
    Inventors: Carsten Benthin, Sven Woop, Ingo Wald
  • Patent number: 10614611
    Abstract: An apparatus and method are described for using tessellation hardware to generate bounding volume hierarchies (BVHs) and perform other ray tracing operations. For example, one embodiment of an apparatus comprises: a shader to output a plurality of tessellation factors and one or more input surfaces; and a tessellation circuit comprising first circuitry and/or logic to tesselate each input surface to generate a new set of primitives and second circuitry and/or logic to concurrently generate a bounding volume hierarchy (BVH) based on the new set of primitives.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: April 7, 2020
    Assignee: Intel Corporation
    Inventors: Carsten Benthin, Gabor Liktor
  • Publication number: 20200105046
    Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
    Type: Application
    Filed: September 27, 2018
    Publication date: April 2, 2020
    Inventors: Ingo Wald, Carsten Benthin, Sven Woop
  • Patent number: 10600231
    Abstract: Embodiments provide for a graphics processing apparatus including a graphics processing unit having bounding volume logic to operate on a compressed bounding volume hierarchy, wherein each bounding volume node stores a parent bounding volume and multiple child bounding volumes that are encoded relative to the parent bounding volume.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 24, 2020
    Assignee: INTEL CORPORATION
    Inventors: Sven Woop, Carsten Benthin, Rasmus Barringer, Tomas G. Akenine-Moller
  • Publication number: 20200074595
    Abstract: Apparatus and method for improving denoising of images generated by a rendering engine such as a ray tracing engine. For example, one embodiment renders a first plurality of images during runtime using a first sample count. Denoising is performed on the first plurality of images during runtime by a machine-learning engine. In addition, a reference region is generated from one or more of the first plurality of images at a second sample count which is greater than the first sample count. The reference region is then used to perform additional runtime training of the machine-learning engine.
    Type: Application
    Filed: August 28, 2018
    Publication date: March 5, 2020
    Inventors: INGO WALD, ATTILA TAMAS AFRA, CARSTEN BENTHIN
  • Patent number: 10580197
    Abstract: An apparatus and method for compressing ray tracing data prior to transmission between nodes. For example, one embodiment of an apparatus comprises: a first node comprising a first ray tracing engine, the first node communicatively coupled to a second node comprising a second ray tracing engine; first compression circuitry coupled to the first ray tracing engine, the first compression circuitry to perform compression on ray tracing data of the first ray tracing engine to produce a first compressed stream of ray tracing data; and interface circuitry to transmit the first compressed stream of ray tracing data from the first node to the second node.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Ingo Wald, Gabor Liktor, Carsten Benthin, Carson Brownlee, Johannes Guenther, Jefferson D. Amstutz
  • Publication number: 20200043218
    Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.
    Type: Application
    Filed: August 6, 2018
    Publication date: February 6, 2020
    Inventors: KARTHIK VAIDYANATHAN, WON-JONG LEE, GABOR LIKTOR, JOHN G. GIERACH, PAWEL MAJEWSKI, PRASOONKUMAR SURTI, CARSTEN BENTHIN, Sven WOOP, THOMAS RAOUX
  • Patent number: 10553010
    Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: February 4, 2020
    Assignee: Intel IP Corporation
    Inventors: Sven Woop, Attila Afra, Carsten Benthin, Ingo Wald, Johannes Guenther
  • Patent number: 10504275
    Abstract: Methods and apparatus relating to more efficient ray tracing of instanced geometry are described. In an embodiment, overlapping instances are unbraided, by not instantiating the entire objects, but instantiating multiple sub-BVH nodes of the objects, which improves rendering performance by reducing overlap of BVH nodes. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 10, 2019
    Assignee: Intel IP Corporation
    Inventors: Ingo Wald, Sven Woop, Carsten Benthin
  • Publication number: 20190318445
    Abstract: Apparatus and method for compressing an acceleration data structure such as a bounding volume hierarchy (BVH). For example, one embodiment of a graphics processing apparatus comprises: one or more cores to execute graphics instructions including instructions to perform ray tracing operations; and compression circuitry to compress lowest level nodes of a hierarchical acceleration data structure comprising a plurality of hierarchically arranged nodes, each of the lowest level nodes comprising pointers to leaf data; the compression circuitry to quantize the lowest level nodes to generate quantized lowest level nodes and to store each quantized lowest level node and associated leaf data without the pointers to the leaf data.
    Type: Application
    Filed: December 28, 2018
    Publication date: October 17, 2019
    Inventors: CARSTEN BENTHIN, SVEN WOOP, INGO WALD
  • Publication number: 20190259195
    Abstract: Embodiments provide for a graphics processing apparatus including a graphics processing unit having bounding volume logic to operate on a compressed bounding volume hierarchy, wherein each bounding volume node stores a parent bounding volume and multiple child bounding volumes that are encoded relative to the parent bounding volume.
    Type: Application
    Filed: March 16, 2018
    Publication date: August 22, 2019
    Applicant: Intel Corporation
    Inventors: Sven WOOP, Carsten BENTHIN, Rasmus BARRINGER, Tomas G. AKENINE-MOLLER
  • Publication number: 20190228560
    Abstract: An apparatus and method for compressing ray tracing data prior to transmission between nodes. For example, one embodiment of an apparatus comprises: a first node comprising a first ray tracing engine, the first node communicatively coupled to a second node comprising a second ray tracing engine; first compression circuitry coupled to the first ray tracing engine, the first compression circuitry to perform compression on ray tracing data of the first ray tracing engine to produce a first compressed stream of ray tracing data; and interface circuitry to transmit the first compressed stream of ray tracing data from the first node to the second node.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 25, 2019
    Inventors: Ingo WALD, Gabor LIKTOR, Carsten BENTHIN, Carson BROWNLEE, Johannes GUENTHER, Jefferson D. AMSTUTZ
  • Publication number: 20190147640
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: October 29, 2018
    Publication date: May 16, 2019
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer KP, Jonathan Kennedy, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Tomer Bar-On, Carsten Benthin, Adam T. Lake, Vasanth Ranganathan, Abhishek R. Appu