Patents by Inventor Carsten Benthin

Carsten Benthin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10229470
    Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: March 12, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Carsten Benthin, Sven Woop, Ingo Wald
  • Patent number: 10204441
    Abstract: An apparatus and method for compressing ray tracing data prior to transmission between nodes. For example, one embodiment of an apparatus comprises: a first node comprising a first ray tracing engine, the first node communicatively coupled to a second node comprising a second ray tracing engine; first compression circuitry coupled to the first ray tracing engine, the first compression circuitry to perform compression on ray tracing data of the first ray tracing engine to produce a first compressed stream of ray tracing data; and interface circuitry to transmit the first compressed stream of ray tracing data from the first node to the second node.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventors: Ingo Wald, Gabor Liktor, Carsten Benthin, Carson Brownlee, Johannes Guenther, Jefferson D. Amstutz
  • Patent number: 10152822
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: December 11, 2018
    Assignee: Intel Corporation
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer KP, Jonathan Kennedy, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Tomer Bar-On, Carsten Benthin, Adam T. Lake, Vasanth Ranganathan, Abhishek R. Appu
  • Publication number: 20180308273
    Abstract: Methods and apparatus relating to more efficient ray tracing of instanced geometry are described. In an embodiment, overlapping instances are unbraided, by not instantiating the entire objects, but instantiating multiple sub-BVH nodes of the objects, which improves rendering performance by reducing overlap of BVH nodes. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: June 29, 2018
    Publication date: October 25, 2018
    Applicant: Intel IP Corporation
    Inventors: Ingo Wald, Sven Woop, Carsten Benthin
  • Publication number: 20180300939
    Abstract: An apparatus and method for efficiently reconstructing a BVH. For example, one embodiment of a method comprises: constructing an object bounding volume hierarchy (BVH) for each object in a scene, each object BVH including a root node and one or more child nodes based on primitives included in each object; constructing a top-level BVH using the root nodes of the individual object BVHs; performing an analysis of the top-level BVH to determine whether the top-level BVH comprises a sufficiently efficient arrangement of nodes within its hierarchy; and reconstructing at least a portion of the top-level BVH if a more efficient arrangement of nodes exists, wherein reconstructing comprises rebuilding the portion of the top-level BVH until one or more stopping criteria have been met, the stopping criteria defined to prevent an entire rebuilding of the top-level BVH.
    Type: Application
    Filed: April 14, 2017
    Publication date: October 18, 2018
    Inventors: CARSTEN BENTHIN, SVEN WOOP
  • Publication number: 20180293783
    Abstract: An apparatus and method for compressing ray tracing data prior to transmission between nodes. For example, one embodiment of an apparatus comprises: a first node comprising a first ray tracing engine, the first node communicatively coupled to a second node comprising a second ray tracing engine; first compression circuitry coupled to the first ray tracing engine, the first compression circuitry to perform compression on ray tracing data of the first ray tracing engine to produce a first compressed stream of ray tracing data; and interface circuitry to transmit the first compressed stream of ray tracing data from the first node to the second node.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 11, 2018
    Inventors: INGO WALD, Gabor Liktor, Carsten Benthin, Carson Brownlee, Johannes Guenther, Jefferson D. Amstutz
  • Publication number: 20180293784
    Abstract: An apparatus and method for performing BVH compression and decompression concurrently with stores and loads, respectively.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 11, 2018
    Inventors: CARSTEN BENTHIN, INGO WALD, GABOR LIKTOR, JOHANNES GUENTHER, ELMOUSTAPHA OULD-AHMED-VALL
  • Publication number: 20180293782
    Abstract: An apparatus and method are described for using tessellation hardware to generate bounding volume hierarchies (BVHs) and perform other ray tracing operations. For example, one embodiment of an apparatus comprises: a shader to output a plurality of tessellation factors and one or more input surfaces; and a tessellation circuit comprising first circuitry and/or logic to tesselate each input surface to generate a new set of primitives and second circuitry and/or logic to concurrently generate a bounding volume hierarchy (BVH) 1521 based on the new set of primitives.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 11, 2018
    Inventors: CARSTEN BENTHIN, GABOR LIKTOR
  • Publication number: 20180286105
    Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: Prasoonkumar Surti, Karthik Vaidyanathan, Atsuo Kuwahara, Hugues Labbe, Sameer KP, Jonathan Kennedy, Joydeep Ray, Travis T. Schluessler, John H. Feit, Nikos Kaburlasos, Jacek Kwiatkowski, Tomer Bar-On, Carsten Benthin, Adam T. Lake, Vasanth Ranganathan, Abhishek R. Appu
  • Publication number: 20180286103
    Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.
    Type: Application
    Filed: April 1, 2017
    Publication date: October 4, 2018
    Inventors: SVEN WOOP, ATTILA TAMAS AFRA, CARSTEN BENTHIN, INGO WALD, JOHANNES GUENTHER
  • Patent number: 10043303
    Abstract: Methods and apparatus relating to more efficient ray tracing of instanced geometry are described. In an embodiment, overlapping instances are unbraided, by not instantiating the entire objects, but instantiating multiple sub-BVH nodes of the objects, which improves rendering performance by reducing overlap of BVH nodes. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: August 7, 2018
    Assignee: Intel IP Corporation
    Inventors: Ingo Wald, Sven Woop, Carsten Benthin
  • Patent number: 9928640
    Abstract: Embodiments provide for a graphics processing apparatus including a graphics processing unit having bounding volume logic to operate on a compressed bounding volume hierarchy, wherein each bounding volume node stores a parent bounding volume and multiple child bounding volumes that are encoded relative to the parent bounding volume.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: March 27, 2018
    Assignee: INTEL CORPORATION
    Inventors: Sven Woop, Carsten Benthin, Rasmus Barringer, Tomas G. Akenine-Moller
  • Publication number: 20180040096
    Abstract: A processing apparatus is described. The apparatus includes a plurality of processing cores, including a first processing core and a second processing core a first field programmable gate array (FPGA) coupled to the first processing core to accelerate execution of graphics workloads processed at the first processing core and a second FPGA coupled to the second processing core to accelerate execution of workloads processed at the second processing core.
    Type: Application
    Filed: August 5, 2016
    Publication date: February 8, 2018
    Applicant: Intel IP Corporation
    Inventors: Carsten Benthin, Sven Woop, Ingo Wald
  • Publication number: 20170372448
    Abstract: While prefetching data for a second fiber, a hierarchical data structure is traversed using a first fiber after deferring traversal for the second fiber. Then context is switched to the second fiber, and the hierarchical data structure is traversed using second fiber while prefetching data for another fiber.
    Type: Application
    Filed: June 28, 2016
    Publication date: December 28, 2017
    Inventors: Ingo Wald, Carsten Benthin, Sven Woop
  • Publication number: 20170287202
    Abstract: Methods and apparatus relating to more efficient ray tracing of instanced geometry are described. In an embodiment, overlapping instances are unbraided, by not instantiating the entire objects, but instantiating multiple sub-BVH nodes of the objects, which improves rendering performance by reducing overlap of BVH nodes. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 5, 2017
    Applicant: Intel IP Corporation
    Inventors: Ingo Wald, Sven Woop, Carsten Benthin
  • Publication number: 20170178387
    Abstract: Embodiments provide for a graphics processing apparatus including a graphics processing unit having bounding volume logic to operate on a compressed bounding volume hierarchy, wherein each bounding volume node stores a parent bounding volume and multiple child bounding volumes that are encoded relative to the parent bounding volume.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Applicant: INTEL CORPORATION
    Inventors: Sven Woop, Carsten Benthin, Rasmus Barringer, Tomas G. Akenine-Moller