Patents by Inventor Chang Wang

Chang Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11946196
    Abstract: The present disclosure discloses an atmospheric-pressure plasma equipment for fabric functional finishing and its application, and belongs to the field of textile printing and dyeing engineering. The atmospheric-pressure plasma equipment, including a discharging system, a grafting instrument and a cloth guider, can conduct continuous plasma treatment on fabrics under an atmospheric pressure, including plasma etching and plasma grafting, which breaks through the disadvantage of batch processing of vacuum plasma equipment. The equipment and method of the present disclosure realize functional finishing of the fabrics in the absence of water, and this finishing process is cost efficient, environmentally friendly, uniform, shorter treatment time and higher reactivity, and applicable to many materials and can keep the bulk properties of the treated substances.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: April 2, 2024
    Assignee: JIANGNAN UNIVERSITY
    Inventors: Chang-E Zhou, Hongwei Wang, Wenkai Shen, Lei Fan, Xin Ju, Guozheng Zhang, Tongxin Yang, Wanning Wang, Chang Sun
  • Publication number: 20240105719
    Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Inventors: Kuo-Cheng Ching, Huan-Chieh Su, Zhi-Chang Lin, Chih-Hao Wang
  • Publication number: 20240107414
    Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Yu-Chieh HUANG, Kuhn-Chang LIN, Jen-Chun CHANG, Wen-Hsin HSIA, Chia-Jou LU, Sheng-Chih WANG, Chenghsin LIN, Yeong Leong CHOO, Chun-Hsiang CHIU, Chihhung HSIEH, Kai-Chun CHENG, Chung Wei LIN
  • Publication number: 20240101557
    Abstract: Disclosed are compounds of Formula I, methods of using the compounds for inhibiting KRAS activity and pharmaceutical compositions comprising such compounds. The compounds are useful in treating, preventing or ameliorating diseases or disorders associated with KRAS activity such as cancer.
    Type: Application
    Filed: July 10, 2023
    Publication date: March 28, 2024
    Inventors: GENCHENG LI, LEI LIU, PEI GAN, CHANG MIN, ALEXANDER SOKOLSKY, XIAOZHAO WANG, QINDA YE, LE ZHAO
  • Patent number: 11940388
    Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: March 26, 2024
    Assignee: IXENSOR CO., LTD.
    Inventors: Yenyu Chen, An Cheng Chang, Tai I Chen, Su Tung Yang, Chih Jung Hsu, Chun Cheng Lin, Min Han Wang, Shih Hao Chiu
  • Patent number: 11940828
    Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: March 26, 2024
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shao-Chang Huang, Yeh-Ning Jou, Ching-Ho Li, Kai-Chieh Hsu, Chun-Chih Chen, Chien-Wei Wang, Gong-Kai Lin, Li-Fan Chen
  • Patent number: 11943939
    Abstract: An integrated circuit (IC) device includes a substrate and a circuit region over the substrate. The circuit region includes at least one active region extending along a first direction, at least one gate region extending across the at least one active region and along a second direction transverse to the first direction, and at least one first input/output (IO) pattern configured to electrically couple the circuit region to external circuitry outside the circuit region. The at least one first IO pattern extends along a third direction oblique to both the first direction and the second direction.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Kai Hsu, Jerry Chang Jui Kao, Chin-Shen Lin, Ming-Tao Yu, Tzu-Ying Lin, Chung-Hsing Wang
  • Publication number: 20240096895
    Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin, Jung-Hung Chang, Lo-Heng Chang, Shi Ning Ju, Guan-Lin Chen
  • Publication number: 20240092318
    Abstract: An end cover assembly, an air cylinder, a tread sweeper and a railway vehicle.
    Type: Application
    Filed: October 9, 2020
    Publication date: March 21, 2024
    Inventors: Qingbing GOU, Anxu WU, Chang FENG, Yuchen ZHANG, Bo WU, Hao XU, Zichen WANG, Xun CHEN, Dongdong WANG, Meng WAN
  • Publication number: 20240097520
    Abstract: An axial flux motor includes a rotor assembly and a stator assembly. The rotor assembly has magnets. The stator assembly has a circuit substrate, segmented iron cores, and a coil. The circuit substrate extends radially. The segmented iron cores are supported on the circuit substrate to be opposite to the magnet in the axial direction. Segmented iron cores arranged in the circumferential direction. A coil is sleeved on a segmented iron core. Holding seats of an insulating material correspond respectively to the segmented iron cores. A holding seat abuts with and covers a segmented iron core from both axial sides and the circumferential direction, and is used for winding the coil. The circuit substrate has slot holes. A slot hole is used for embedding and positioning a portion of a holding seat that protrudes more towards one axial side than the coil.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 21, 2024
    Inventors: Keng-Chang WU, Guo-Jhih YAN, Hsiu-Ying LIN, Kuo-Min WANG
  • Publication number: 20240092930
    Abstract: The present invention provides an antibody binding a human tumor-associated calcium signal sensor 2 (Trop-2) protein or fragments thereof, and use of the antibody or fragments thereof in preventing or treating diseases. The antibody or fragments thereof of the present invention can effectively bind to the human Trop-2 protein, and have internalization activity, and the internalization activity is enhanced after ADC drug labeling, and the in vivo efficacy and safety of a mouse model are not lower than those of a control antibody.
    Type: Application
    Filed: October 12, 2020
    Publication date: March 21, 2024
    Inventors: Shuang WANG, Rongjuan WANG, Shasha JIAO, Chang ZHANG, Jiao ZHANG, Dadi ZENG, Jinchao ZHANG
  • Patent number: 11934027
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 11935794
    Abstract: A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang, Zhi-Chang Lin, Li-Zhen Yu
  • Publication number: 20240086590
    Abstract: An adaptive grid generating method includes obtaining a first three-dimensional grid of a target structure; importing the first three-dimensional grid into a computer-aided engineering software to obtain a first two-dimensional planar grid; importing the first two-dimensional planar grid into a grid cleaning software to obtain a second two-dimensional planar grid; and importing the second two-dimensional planar grid into the computer-aided engineering software to obtain a second three-dimensional grid.
    Type: Application
    Filed: June 12, 2023
    Publication date: March 14, 2024
    Applicants: Inventec (Pudong) Technology Corp., Inventec Corporation
    Inventors: Hsueh-Liang Chen, Chen-Chou Huang, I-Chang Wang, Tzung-Shian Hung
  • Publication number: 20240088225
    Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventors: Su-Hao Liu, Wen-Yen Chen, Li-Heng Chen, Li-Ting Wang, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo, Ying-Lang Wang
  • Publication number: 20240088145
    Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu, Chih-Hao Wang, Kuo-Cheng Ching
  • Publication number: 20240089581
    Abstract: An electronic system including an image sensor, a face detection engine, an eye detection engine and an eye protection engine is provided. The image sensor captures an image. The face detection engine recognizes a user face in the image. The eye detection engine recognizes user eyes in the image. The eye protection engine turns off a display device when the user eyes are recognized in the image but the user face is not recognized in the image.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: HAN-CHANG LIN, GUO-ZHEN WANG, NIEN-TSE CHEN
  • Publication number: 20240090213
    Abstract: A method of forming a semiconductor memory device includes simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle of a deposition process and an etch process, wherein the first HAR structure has a critical dimension (CD) of between 150 nm and 250 nm, and the second HAR structure has a CD of between 250 nm and 400 nm.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 14, 2024
    Inventors: Jialiang WANG, Soonil LEE, Eswaranand VENKATASUBRAMANIAN, Chang Seok KANG, Sanjay G. KAMATH, Abhijit B. MALLICK, Srinivas GUGGILLA, Amy CHILD, Sung-Kwan KANG, Balasubramanian PRANATHARTHIHARAN
  • Patent number: 11930681
    Abstract: A display panel and a display device are provided. The display panel includes a first color sub-pixels and a second color sub-pixel. The first color sub-pixel includes a first effective light emitting region, the second color sub-pixel includes a second effective light emitting region, an area of the second effective light emitting region is smaller than that of the first effective light emitting region. The first color sub-pixel includes a first color light emitting layer, the second color sub-pixel includes a second color light emitting layer, an area ratio between orthographic projections of the first color light emitting layer and the first effective light emitting region on the base substrate is less than an area ratio between orthographic projections of the second color light emitting layer and the second effective light emitting region on the base substrate.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: March 12, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hongli Wang, Chang Luo, Lei Chen, Kening Zheng, Chen Xu
  • Patent number: D1020147
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: March 26, 2024
    Assignees: JIANGSU MIDEA CLEANING APPLIANCES CO., LTD., MIDEA GROUP CO., LTD.
    Inventors: Jin Wang, Hyun Seon Shin, Lu Wang, Chang Liu, Pei Cao, Gang Liu, Jian Xu